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S3C9498/F9498
8-BIT CMOS MICROCONTROLLER USER'S MANUAL Revision 1
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Important Notice
The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others. Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. S3C9498/F9498 8-Bit CMOS Microcontroller User's Manual, Revision 1 Publication Number: 21-S3-C9498/F9498-102004 (c) 2004 Samsung Electronics All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics. Samsung Electronics' microcontroller business has been awarded full ISO-14001 certification (BVQ1 Certificate No. 9330). All semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives. Samsung Electronics Co., Ltd. San #24 Nongseo-Ri, Giheung- Eup Yongin-City, Gyeonggi-Do, Korea C.P.O. Box #37, Suwon 449-900 TEL: FAX: (82)-(031)-209-1934 (82) (331) 209-1889 "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts. Samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur. Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application, the Buyer shall indemnify and hold Samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product.
Home-Page URL: Http://www.samsungsemi.com/ Printed in the Republic of Korea
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Preface
The S3C9498/F9498 Microcontroller User's Manual is designed for application designers and programmers who are using the S3C9498/F9498 microcontroller for application development. It is organized in two parts: Part I Programming Model Part II Hardware Descriptions
Part I contains software-related information to familiarize you with the microcontroller's architecture, programming model, instruction set, and interrupt structure. It has six chapters: Chapter 1 Chapter 2 Chapter 3 Product Overview Address Spaces Addressing Modes Chapter 4 Chapter 5 Chapter 6 Control Registers Interrupt Structure SAM88RCRI Instruction Set
Chapter 1, "Product Overview," is a high-level introduction to the S3C9498/F9498 with a general product description, and detailed information about individual pin characteristics and pin circuit types. Chapter 2, "Address Spaces," explains the S3C9498/F9498 program and data memory, internal register file, and mapped control registers, and explains how to address them. Chapter 2 also describes working register addressing, as well as system and user-defined stack operations. Chapter 3, "Addressing Modes," contains detailed descriptions of the six addressing modes that are supported by the CPU. Chapter 4, "Control Registers," contains overview tables for all mapped system and peripheral control register values, as well as detailed one-page descriptions in standard format. You can use these easy-to-read, alphabetically organized, register descriptions as a quick-reference source when writing programs. Chapter 5, "Interrupt Structure," describes the S3C9498/F9498 interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in part II. Chapter 6, "SAM88RCRI Instruction Set," describes the features and conventions of the instruction set used for all S3C9-series microcontrollers. Several summary tables are presented for orientation and reference. Detailed descriptions of each ins truction are presented in a standard format. Each instruction description includes one or more practical examples of how to use the instruction when writing an application program. A basic familiarity with the information in part I will help you to understand the hardware module descriptions in Part II. If you are not yet familiar with the SAM88RCRI product family and are reading this manual for the first time, we recommend that you first read chapters 1-3 carefully. Then, briefly look over the detailed information in chapters 4, 5, and 6. Later, you can reference the information in part I as necessary. Part II contains detailed information about the peripheral components of the S3C9498/F9498 microcontrollers. Also included in part II are electrical, mechanical, MTP, and development tools data. It has 14 chapters: Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Chapter 13 Clock Circuit RESET and Power-Down I/O Ports Basic Timer 8-bit Timer A/B 16-bit Timer 1 Timer 0 Chapter 14 Chapter 15 Chapter 16 Chapter 17 Chapter 18 Chapter 19 Chapter 20 Chapter 21 UART Serial I/O Interface PWM ADC Electrical Data Mechanical Data MTP Development Tools
Two order forms are included at the back of this manual to facilitate customer order for S3C9498/F9498 microcontroller: the Mask ROM Order Form, and the Mask Option Selection Form. You can photocopy these forms, fill them out, and then forward them to your local Samsung Sales Representative.
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Table of Contents
Part I -- Programming Model
Chapter 1 Product Overview
S3C9-Series Microcontrollers ...............................................................................................................1-1 S3C9498/F9498 Microcontroller ............................................................................................................1-1 MTP ...................................................................................................................................................1-1 Features................................ ................................ ................................ ................................ .............1-2 Block Diagram ....................................................................................................................................1-3 Pin Assignment...................................................................................................................................1-4 Pin Descriptions..................................................................................................................................1-6 Pin Circuits................................ ................................ ................................ ................................ .........1-8
Chapter 2
Address Spaces
Overview................................ ................................ ................................ ................................ .............2-1 Program Memory (ROM)......................................................................................................................2-2 Program Memory (ROM)......................................................................................................................2-2 Register Architecture ...........................................................................................................................2-4 Common Working Register Area (C0H-CFH) ................................ ................................ .........................2-6 System Stack................................ ................................ ................................ ................................ .....2-7
Chapter 3
Addressing Modes
Overview................................ ................................ ................................ ................................ .............3-1 Register Addressing Mode (R)..............................................................................................................3-2 Indirect Register Addressing Mode (IR)..................................................................................................3-3 Indexed Addressing Mode (X) ...............................................................................................................3-7 Direct Address Mode (DA)....................................................................................................................3-10 Direct Address Mode (Continued)..........................................................................................................3-11 Relative Address Mode (RA)................................ ................................ ................................ .................3-12 Immediate Mode (IM) ...........................................................................................................................3-13
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Table of Contents (Continued)
Chapter 4 Control Registers
Overview................................ ................................ ................................ ................................ .............4-1
Chapter 5
Interrupt Structure
Overview................................ ................................ ................................ ................................ .............5-1 Interrupt Processing Control Points ...............................................................................................5-1 Enable/Disable Interrupt Instructions (EI, DI) ..................................................................................5-2 Interrupt Pending Function Types..................................................................................................5-2 Interrupt Priority...........................................................................................................................5-2 Interrupt Source SERvice Sequence..............................................................................................5-3 Interrupt Service Routines ................................ ................................ ................................ .............5-3 Generating interrupt Vector Addresses ..........................................................................................5-3 S3C9498/F9498 Interrupt Structure ...............................................................................................5-4
Chapter 6
SAM88RCRI Instruction Set
Overview................................ ................................ ................................ ................................ .............6-1 Register Addressing ....................................................................................................................6-1 Addressing Modes.......................................................................................................................6-1 Flags Register (FLAGS)...............................................................................................................6-4 Flag Descriptions ........................................................................................................................6-4 Instruction Set Notation................................................................................................................6-5 Condition Codes..........................................................................................................................6-9 Instruction Descriptions ................................................................................................................6-10
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Table of Contents (Continued)
Part II -- Hardware Descriptions
Chapter 7 Clock Circuit
Overview................................ ................................ ................................ ................................ .............7-1 System Clock Circuit...................................................................................................................7-1 Clock Status During Power-Down Modes .......................................................................................7-2 System Clock Control Register (CLKCON)................................ ................................ .....................7-3
Chapter 8
RESET and Power-Down
System Reset ................................ ................................ ................................ ................................ .....8-1 Overview................................ ................................ ................................ ................................ .....8-1 Normal Mode Reset Operation......................................................................................................8-1 Hardware Reset Values ................................................................................................................8-2 Power-Down Modes................................ ................................ ................................ .............................8-4 Stop Mode..................................................................................................................................8-4 Idle Mode....................................................................................................................................8-5
Chapter 9
I/O Ports
Overview................................ ................................ ................................ ................................ .............9-1 Port Data Registers ................................ ................................ ................................ .....................9-2 Port 0................................ ................................ ................................ ................................ .........9-3 Port 1................................ ................................ ................................ ................................ .........9-5 Port 2................................ ................................ ................................ ................................ .........9-9 Port 3................................ ................................ ................................ ................................ .........9-12
Chapter 10
Basic Timer
Overview................................ ................................ ................................ ................................ .............10-1 BASic timer (Bt)..................................................................................................................................10-2 Basic Timer Control Register (BTCON)..........................................................................................10-2 Basic Timer Function Description..................................................................................................10-3
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Table of Contents (Continued)
Chapter 11 8-bit Timer A/B
8-bit timer A ........................................................................................................................................11-1 Overview................................ ................................ ................................ ................................ .....11-1 Function Description ....................................................................................................................11-2 Timer A Control Register (TACON) ................................................................................................11-3 Timer A Data Register (TADATA)..................................................................................................11-4 Block Diagram ............................................................................................................................11-5 8-Bit Timer B.......................................................................................................................................11-6 Overview................................ ................................ ................................ ................................ .....11-6
Chapter 12
16-bit Timer 1
Overview................................ ................................ ................................ ................................ .............12-1 Function Description ....................................................................................................................12-2 Timer 1 Control Register (T1CON) ................................ ................................ ................................ .12-3 Block Diagram ............................................................................................................................12-5
Chapter 13
Timer 0
One 16-Bit Timer Mode (Timer 0) ..........................................................................................................13-1 Overview................................ ................................ ................................ ................................ .....13-1 Function Description ....................................................................................................................13-1 Block Diagram ....................................................................................................................................13-3 Two 8-Bit Timers Mode (Timer C and D)................................ ................................ ................................ .13-4 Overview................................ ................................ ................................ ................................ .....13-4 Function Description ....................................................................................................................13-7
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Table of Contents (Continued)
Chapter 14 UART
Overview................................ ................................ ................................ ................................ .............14-1 Programming Procedure...............................................................................................................14-1 UART Control Register (UARTCON) ..............................................................................................14-2 UART Interrupt Pending Register (UARTPND) ................................................................................14-3 Uart Data Register (UDATA) ................................ ................................ ................................ .........14-4 Uart Baud Rate Data Register (BRDATA ).......................................................................................14-4 Baud Rate Calculations ................................................................................................................14-5 Block Diagram ....................................................................................................................................14-6 Uart Mode 0 Function Description................................ ................................ ................................ .14-7 Uart Mode 1 Function Description................................ ................................ ................................ .14-8 Uart Mode 2 Function Description................................ ................................ ................................ .14-9 Serial Communication For Multiprocessor Configurations ................................................................14-11
Chapter 15
Serial I/O Interface
Overview................................ ................................ ................................ ................................ .............15-1 Programming Procedure...............................................................................................................15-1 Serial I/O Control Registers (SIOCON)...........................................................................................15-2 SIO Prescaler Register (S IOPS) ...................................................................................................15-3
Chapter 16
PWM
Overview................................ ................................ ................................ ................................ .............16-1 Function Description ............................................................................................................................16-1 PWM ................................ ................................ ................................ ................................ .........16-1 PWM Control Register (PWMCON)...............................................................................................16-5
Chapter 17
A/D Converter
Overview................................ ................................ ................................ ................................ .............17-1 Function Description ............................................................................................................................17-1 Conversion Timing .......................................................................................................................17-2 A/D Converter Control Register (ADCON).......................................................................................17-2 Internal Reference Voltage Levels..................................................................................................17-3 Block Diagram ....................................................................................................................................17-4 Internal A/D Conversion Procedure ................................................................................................17-5
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Table of Contents (Continued)
Chapter 18 Electrical Data
Overview................................ ................................ ................................ ................................ .............18-1
Chapter 19
Mechanical Data
Overview................................ ................................ ................................ ................................ .............19-1
Chapter 20
MTP
Overview................................ ................................ ................................ ................................ .............20-1
Chapter 21
Development Tools
Overview................................ ................................ ................................ ................................ .............21-1 SHINE ........................................................................................................................................21-1 SASM ........................................................................................................................................21-1 SAMA Assembler........................................................................................................................21-1 HEX2ROM ..................................................................................................................................21-1 Target Boards ................................ ................................ ................................ .............................21-2 TB9498 Target Board ...................................................................................................................21-3
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List of Figures
Figure Number 1-1 1-2 1-3 1-4 1-5 1-7 1-6 1-8 1-9 1-10 1-11 2-1 2-2 2-3 2-4 2-5 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 Title Page Number
S3C9498/F9498 Block Diagram ........................................................................................1-3 S3C9498/F9498 Pin Assignment (32-DIP, 32-SOP) ............................................................1-4 S3C9498/F9498 Pin Assignment (28-SOP)........................................................................1-4 S3C9498/F9498 Pin Assignment (30-SDIP) .......................................................................1-5 Pin Circuit Type B (RESET)..............................................................................................1-8 Pin Circuit Type C ...........................................................................................................1-8 Pin Circuit Type D-1................................ ................................ ................................ .........1-8 Pin Circuit Type D-2................................ ................................ ................................ .........1-8 Pin Circuit Type E ...........................................................................................................1-9 Pin Circuit Type E-1................................ ................................ ................................ .........1-9 Pin Circuit Type E-2................................ ................................ ................................ .........1-10 Program Memory Address Space................................ ................................ .....................2-2 Smart Option ..................................................................................................................2-3 Internal Register File Organization................................ ................................ .....................2-5 16-Bit Register Pairs........................................................................................................2-6 Stack Operations ............................................................................................................2-7 Register Addressing ........................................................................................................3-2 Working Register Addressing ...........................................................................................3-2 Indirect Register Addressing to Register File......................................................................3-3 Indirect Register Addressing to Program Memory ...............................................................3-4 Indirect Working Register Addressing to Register File........................................................3-5 Indirect Working Register Addressing to Program or Data Memory.......................................3-6 Indexed Addressing to Register File..................................................................................3-7 Indexed Addressing to Program or Data Memory with Short Offset.......................................3-8 Indexed Addressing to Program or Data Memory ................................................................3-9 Direct Addressing for Load Instructions..............................................................................3-10 Direct Addressing for Call and Jump Instructions ................................................................3-11 Relative Addressing................................ ................................ ................................ .........3-12 Immediate Addressing ................................ ................................ ................................ .....3-13
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List of Figures (Continued)
Figure Number 4-1 5-1 5-2 5-3 6-1 7-1 7-2 7-3 9-1 9-2 9-3 9-4 9-5 9-6 9-7 10-1 10-2 10-3 11-1 11-2 11-3 11-4 11-5 11-6 11-7 Title Page Number
Register Description Format ................................ ................................ .............................4-3 S3C9-Series Interrupt Type...............................................................................................5-1 Interrupt Function Diagram ...............................................................................................5-2 S3F9498 Interrupt Structure..............................................................................................5-4 System Flags Register (FLAGS).......................................................................................6-4 Main Oscillator Circuit (Crystal or Ceramic Oscillator) ................................ .........................7-1 System Clock Control Register (CLKCON)................................ ................................ .........7-3 STOP Control Register (STPCON) ....................................................................................7-3 Port 0 High-Byte Control Register (P0CON) .......................................................................9-4 Port 1 High-Byte Control Register (P1CONH) ................................ ................................ .....9-6 Port 1 Low-Byte Control Register (P1CONL) ......................................................................9-7 Port 1 Interrupt Control Register P1PND) ...........................................................................9-8 Port 2 High-Byte Control Register (P2CONH) ................................ ................................ .....9-10 Port 2 Low-Byte Control Register (P2CONL) ......................................................................9-11 Port 3 High-Byte Control Register (P3CON) .......................................................................9-13 Basic Timer Control Register (BTCON)..............................................................................10-2 Oscillation Stabilization Time on RESET ...........................................................................10-4 Oscillation Stabilization Time on STOP Mode Release........................................................10-5 Timer A Control Register (TACON) ....................................................................................11-3 Timer interrupts Pending Register (TINTPND) ................................ ................................ .....11-4 Timer A Data Register (TADATA)......................................................................................11-4 Timer A Functional Block Diagram ....................................................................................11-5 Timer B Functional Block Diagram ....................................................................................11-6 Timer B Control Register (TBCON) ....................................................................................11-7 Timer B Data Registers (TBDATA) ....................................................................................11-7
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List of Figures (Continued)
Figure Number 12-1 12-2 12-3 13-1 13-2 13-3 13-4 13-5 13- 6 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 15-1 15-2 15-3 15-4 15-5 15-6 16-1 16-2 16-3 16-4 Title Page Number
Timer 1 Control Register (T1CON) ................................ ................................ .....................12-3 Timer A/B/D and Timer 1 Pending Register (TINTPND) ........................................................12-4 Timer 1 Functional Block Diagram................................ ................................ .....................12-5 Timer 0 Control Register (TCCON)................................ ................................ .....................13-2 Timer 0 Functional Block Diagram................................ ................................ .....................13-3 Timer C Control Register (TCCON) ....................................................................................13-5 Timer D Control Register (TDCON) ....................................................................................13-6 Timer C and B Function Block Diagram ................................ ................................ .............13-8 Timer D PWM Function Block Diagram ................................ ................................ .............13-9 UART Control Register (UARTCON) ..................................................................................14-2 UART Interrupt Pending Register (UARTPND) ....................................................................14-3 UART Data Register (UDATA)...........................................................................................14-4 UART Baud Rate Data Register (BRDATA) ........................................................................14-4 UART Functional Block Diagram .......................................................................................14-6 Timing Diagram for UART Mode 0 Operation ......................................................................14-7 Timing Diagram for UART Mode 1 Operation ......................................................................14-8 Timing Diagram for UART Mode 2 Operation ......................................................................14-9 Timing Diagram for UART Mode 3 Operation ......................................................................14-10 Connection Example for Multiprocessor Serial Data Communications...................................14-12 Serial I/O Interface Control Register (SIOCON) ...................................................................15-2 SIO Pre-Scaler Register (SIOPS)......................................................................................15-3 IO Functional Block Diagram ............................................................................................15-3 Serial I/O Timing in Transmit-Receive Mode (Tx at falling, SIOCON.4 = 0) .............................15-4 Serial I/O Timing in Transmit-Receive Mode (Tx at rising, SIOCON.4 = 1) .............................15-4 Serial I/O Timing in Receive-Only Mode................................ ................................ .............15-5 12-Bit PWM Basic Waveform ...........................................................................................15-3 12-Bit Extended PWM Waveform......................................................................................15-4 PWM/Capture Module Control Register (PWMCON) ...........................................................15-5 PWM/Capture Module Functional Block Diagram ...............................................................15-6
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List of Figures (Continued)
Figure Number 17-1 17-2 17-3 17-4 18-1 18-2 18-3 18-4 18-5 19-1 19-2 19-3 20-1 20-2 20-3 21-1 21-2 21-3 21-4 21-5 Title Page Number
A/D Converter Control Register (ADCON)...........................................................................17-2 A/D Converter Data Register (ADDATAH/L) ........................................................................17-3 A/D Converter Functional Block Diagram ...........................................................................17-4 Recommended A/D Converter Circuit for Highest Absolute Accuracy....................................17-5 Input Timing Measurement Points................................ ................................ .....................18-4 Operating Voltage Range (S3C9498/F9498) .......................................................................18-5 Schimtt Trigger Input Characteristic Diagram......................................................................18-5 Stop Mode Release Timing When Initiated by a RE SET......................................................18-7 Definition of DLE and ILE..................................................................................................18-9 32-SOP-450A Package Dimensions..................................................................................19-1 28-SOP-375 Package Dimensions ....................................................................................19-2 30-Pin SDIP Package Dimensions ....................................................................................19-3 Pin Assignment Diagram (32-Pin Package)........................................................................20-1 Pin Assignment Diagram (30-Pin Package)........................................................................20-2 Pin Assignment Diagram (28-Pin Package)........................................................................20-2 SMDS+ or SK-1000 Product Configuration................................ ................................ .........21-2 TB9498 Target Board Configuration ...................................................................................21-3 DIP Switch for Smart Option................................ ................................ .............................21-5 44-Pin Connector for TB9498 ............................................................................................21-6 S3C9498/F9498 Probe Adapter for 40pin Connector Package..............................................21-6
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List of Tables
Table Number 1-1 1-2 2-1 4-1 6-1 6-2 6-3 6-4 6-5 6-6 8-1 9-1 9-2 14-1 16-1 16-2 Title Page Number
Pin Descriptions of 28-SOP (32-SOP, 32-SDIP / 30-SDIP)..................................................1-6 Pin Descriptions of 28-SOP (32-SOP, 32-SDIP / 30-SDIP)..................................................1-7 Register Type Summary...................................................................................................2-4 System and Peripheral Registers......................................................................................4-1 Instruction Group Summary..............................................................................................6-2 Flag Notation Conventions ................................................................................................6-5 Instruction Set Symbols ...................................................................................................6-5 Instruction Notation Conventions .......................................................................................6-6 Opcode Quick Reference................................ ................................ ................................ .6-7 Condition Codes..............................................................................................................6-9 S3C9498/F9498 Register Values after RESET ...................................................................8-2 S3C9498/F9498 Port Configuration Overview......................................................................9-1 Port Data Register Summary ............................................................................................9-2 Commonly Used Baud Rates Generated by 8-bit BRDATA..................................................14-5 PWM Control and Data Registers ................................ ................................ .....................16-2 PWM output "stretch" Values for Extension Registers PWMEX...........................................16-3
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List of Tables
Table Number 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 20-1 21-1 21-2 Title
(Continued)
Page Number
Absolute Maximum Ratings..............................................................................................18-2 D.C. Electrical Characteristics..........................................................................................18-3 A.C. Electrical Characteristics..........................................................................................18-4 Oscillator Characteristics................................ ................................ ................................ .18-6 Oscillation Stabilization Time............................................................................................18-6 Data Retention Supply Voltage in Stop Mode................................ ................................ .....18-7 LVR(Low Voltage Reset) Circuit Characteristics ................................................................18-7 A/D Converter Electrical Characteristics ............................................................................18-8 Descriptions of Pins Used to Read/Write the Flash ROM....................................................20-3 Power Selection Settings for TB9498................................ ................................ .................21-4 The SMDS2+ Tool Selection Setting ................................ ................................ .................21-4
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List of Register Descriptions
Register Identifier ADCON BTCON CLKCON FLAGS P0CON P1CONH P1CONL P1INT P2CONH P2CONL P3CON PWMCON SIOCON SP STPCON SYM T1CON TACON TBCON TCCON TCNTSEL TDCON TINTPND UARTCON UARTPND Full Register Name Page Number
A/D Converter Control Register ................................ ................................ .........................4 Basic Timer Control Register ............................................................................................5 System Clock Control Register ................................ ................................ .........................6 System Flags Register......................................................................................................................................7 Port 0 Control Register .....................................................................................................................................8 Port 1 Control Register (High Byte)...............................................................................................................9 Port 1 Control Register (Low Byte) ................................................................................................................10 Port 1 Interrupt Control Register .....................................................................................................................11 Port 2 Control Register (High Byte)...............................................................................................................12 Port 2 Control Register (Low Byte) ................................................................................................................13 Port 3 Control Register ......................................................................................................................................14 PWM Control Register ................................ ................................ ................................ .....15 Serial I/O Module Control Registers..............................................................................................................16 Stack Pointer ..............................................................................................................17 Stop Control Register......................................................................................................................................... 17 System Mode Register .................................................................................................................................... 18 Timer 1 Control Register................................................................................................................................... 19 Timer A Control Register................................................................................................................................... 20 Timer B Control Register................................................................................................................................... 21 Timer C Control Register................................................................................................................................... 22 Timer Counter read selection Register ......................................................................................................... 23 Timer D Control Register................................................................................................................................... 24 Interrupt Pending Register ................................................................................................................................ 25 UART Control Register ...................................................................................................................................... 26 UART Pending and parity control................................................................................................................... 27
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List of Instruction Descriptions
Instruction Mnemonic ADC ADD AND CALL CCF CLR COM CP DEC DI EI IDLE INC IRET JP JR LD LDC/LDE LDCD/LDED LDCI/LDEI NOP OR POP PUSH RCF RET RL RLC RR RRC SBC SCF SRA STOP SUB TCM TM XOR Full Instruction Name Page Number
Add With Carry .......................................................................................6-11 Add ........................................................................................................6-12 Logical AND............................................................................................6-13 Call Procedure ........................................................................................6-14 Complement Carry Flag ...........................................................................6-15 Clear......................................................................................................6-16 Complement ...........................................................................................6-17 Compare................................ ................................ ................................ .6-18 Decrement..............................................................................................6-19 Disable Interrupts ....................................................................................6-20 Enable Interrupts................................ ................................ .....................6-21 Idle Operation..........................................................................................6-22 Increment ...............................................................................................6-23 Interrupt Return .......................................................................................6-24 Jump......................................................................................................6-25 Jump Relative..........................................................................................6-26 Load.......................................................................................................6-27 Load Memory..........................................................................................6-29 Load Memory and Decrement...................................................................6-31 Load Memory and Increment ....................................................................6-32 No Operation...........................................................................................6-33 Logical OR..............................................................................................6-34 Pop From Stack......................................................................................6-35 Push To Stack ........................................................................................6-36 Reset Carry Flag................................ ................................ .....................6-37 Return ....................................................................................................6-38 Rotate Left..............................................................................................6-39 Rotate Left Through Carry ................................ ................................ .........6-40 Rotate Right............................................................................................6-41 Rotate Right Through Carry ......................................................................6-42 Subtract with Carry..................................................................................6-43 Set Carry Flag................................ ................................ .........................6-44 Shift Right Arithmetic ...............................................................................6-45 Stop Operation ........................................................................................6-46 Subtract ................................ ................................ ................................ .6-47 Test Complement Under Mask..................................................................6-48 Test Under Mask................................ ................................ .....................6-49 Logical Exclusive OR ...............................................................................6-50
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S3C9498/F9498
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
S3C9-SERIES MICROCONTROLLERS
Samsung's SAM88RCRI family of 8-bit single-chip CMOS microcontrollers offer a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. A address/data bus architecture and a large number of bit-configurable I/O ports provide a flexible programming environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating modes are included to support real-time operations.
S3C9498/F9498 MICROCONTROLLER
The S3C9498/F9498single-chip CMOS microcontrollers are fabricated using the highly advanced CMOS process technology based on Samsung's latest CPU architecture. The S3C9498/F9498 is a microcontroller with a 8K-byte multi time programmable ROM embedded. Using a proven modular design approach, Samsung engineers have successfully developed the S3C9498/F9498 by integrating the following peripheral modules with the powerful SAM88 RCRI core: -- Four configurable I/O ports (22 pins / 24pins / 26pin) -- Fifteen interrupt sources with one vector and one interrupt level -- One watchdog timer function (Basic Timer overflow ) -- One 8-bit basic timer for oscillation stabilization -- Four 8-bit timer/counter with time interval, PWM, and Capture mode (Timer C and Timer D can be used for 16-bit Timer 0) -- One 16-bit timer/counter with three operating modes; Interval timer, Capture and PWM mode (If Timer C and Timer D is used for Timer 0, S3C9498/F9498 has two 16-bit Timer; Timer 0 and Timer 1) -- Analog to digital converter with 8 input channels and 10-bit resolution -- One asynchronous UART and one synchronous SIO The S3C9498/F9498 microcontroller is ideal for use in a wide range of home applications requiring simple timer/counter, ADC, etc. They are currently available in 32-pin SOP/SDIP, 28-pin SOP, 30-pin SDIP package.
MTP
The S3C9498/F9498 has on-chip 8-Kbyte multi time programmable (MTP) ROM instead of masked ROM. The S3C9498/F9498 is fully compatible to the S3C9498, in function, in D.C. electrical characteristics and in pin configuration.
1-1
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PRODUCT OVERVIEW
S3C9498/F9498
FEATURES
CPU
*
Timer 0 Timer/Counters
* *
SAM88RCRI CPU core
The programmable 8-bit timer/counters Configurable as on 16-bit timer/counters
Memory
* * *
208-byte general purpose register (RAM) 8K-byte internal mask program memory 8K-byte internal multi time program memory (S3C9498/F9498) Half-Flash
PWM module
* *
12-bit PWM (Max: 250KHz) 6-bit base + 6-bit extension frame
A/D Converter Oscillation Sources
* * * *
Crystal, Ceramic CPU clock divider (1/1, 1/2, 1/8, 1/16)
Eight analog input channels 25us conversion speed at 8MHz fADC clock
Serial I/O Instruction Set
* * * *
41 instructions IDLE and STOP instructions added for powerdown modes
One synchronous serial I/O module Selectable transmit and receive rates.
Asynchronous UART
* *
Instruction Execution Time
*
500 ns at 8-MHz fOSC (minimum)
Programmable baud rate generator Support serial data transmit/receive operations with 8-bit, 9-bit UART
Interrupts
*
Low Voltage Reset (LVR)
* *
15 interrupt sources with one vector / one level
I/O Ports
*
Low Voltage Check to make system reset VLVR = 3V (by smart option)
Total 22/24/26 bit-programmable pins
Operating Temperature Range
*
Basic Timer
*
-25 C to + 85 C
One programmable 8-bit basic timer (BT) for Oscillation stabilization control
Operating Voltage Range
*
3 V to 5.5 V (LVR) 2.2 V to 5.5V (No LVR)
Timers
*
* *
One 8-bit timer/counter (Timer A) with three operating modes; Interval mode, capture mode and PWM mode One 8-bit timer/counter (Timer B) Carrier frequency (or PWM) generator One 16-bit capture timer/counter (Timer 1) with three operating modes; Interval mode, Capture mode for pulse period or duty and PWM mode.
Package Type * 28-pin SOP, 30-pin SDIP, 32-pin SDIP/SOP
.
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S3C9498/F9498
PRODUCT OVERVIEW
BLOCK DIAGRAM
PWM
(ADC0-7)
PW M XIN XOUT nRESET
A/D Port 0 P0.0P0.2
OSC/nRESET I/O Port and Interrupt Control Port 1 P1.0P1.7
8-Bit Basic Timer TAOUT TACK TACAP 8-Bit Timer /Counter A 16-bit Timer /Counter 1 8-Bit Timer /Counter B 8-Bit timer C/D
Port 2 SAM88RCRI CPU
P2.0P2.7
Port 3 8-Kbyte ROM 208-Byte RAM
P3.0P3.6 SI SO SCK TXD RXD
TBOUT
SIO UART
TDOUT
Figure 1-1. S3C9498/F9498 Block Diagram
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PRODUCT OVERVIEW
S3C9498/F9498
PIN ASSIGNMENT
VSS XOUT XIN (Vpp)TEST RxD/P0.0 TxD/P0.1 nRESET/P0.2 P3.3 P3.4 AVREF INT0/ADC0/P1.0 INT1/ADC1/P1.1 ADC2/P1.2 ADC3/P1.3 ADC4/P1.4 ADC5/P1.5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
S3F9498
(Top View)
32-SOP 32-SDIP
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VDD P3.2/SCK(SCLK) P3.1/SO(SDAT) P3.0/SI P2.7/PWM P2.6/T1CAP P2.5/T1OUT P3.6 P3.5 P2.4/T1CK P2.3/TBOUT P2.2/TACAP P2.1/TACK P2.0/TAOUT P1.7/ADC7 P1.6/ADC6/TDOUT
Figure 1-2. S3C9498/F9498 Pin Assignment (32-DIP, 32-SOP)
VSS XOUT XIN (Vpp)TEST RxD/P0.0 TxD/P0.1 nRESET/P0.2 AVREF INT0/ADC0/P1.0 INT1/ADC1/P1.1 ADC2/P1.2 ADC3/P1.3 ADC4/P1.4 ADC5/P1.5
1 2 3 4 5 6 7 8 9 10 11 12 13 14
S3F9498
(Top View) 28-SOP
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDD P3.2/SCK (SCLK) P3.1/SO (SDAT) P3.0/SI P2.7/PWM P2.6/T1CAP P2.5/T1OUT P2.4/T1CK P2.3/TBOUT P2.2/TACAP P2.1/TACK P2.0/TAOUT P1.7/ADC7 P1.6/ADC6/TDOUT
Figure 1-3. S3C9498/F9498 Pin Assignment (28-SOP)
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S3C9498/F9498
PRODUCT OVERVIEW
PIN ASSIGNMENT
VSS XOUT XIN (Vpp)TEST RxD/P0.0 TxD/P0.1 nRESET/P0.2 P3.3 AVREF INT0/ADC0/P1.0 INT1/ADC1/P1.1 ADC2/P1.2 ADC3/P1.3 ADC4/P1.4 ADC5/P1.5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
S3F9498
(Top View)
30-SDIP
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VDD P3.2/SCK (SCLK) P3.1/SO (SDAT) P3.0/SI P2.7/PWM P2.6/T1CAP P2.5/T1OUT P3.5 P2.4/T1CK P2.3/TBOUT P2.2/TACAP P2.1/TACK P2.0/TAOUT P1.7/ADC7 P1.6/ADC6/TDOUT
Figure 1-4. S3C9498/F9498 Pin Assignment (30-SDIP)
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PRODUCT OVERVIEW
S3C9498/F9498
PIN DESCRIPTIONS
Table 1-1. Pin Descriptions of 28-SOP (32-SOP,32-SDIP / 30-SDIP) Pin Names P0.0, P0.1 P0.2 Pin Type I/O Pin Description I/O port with bit-programmable pins. Configurable to input or push-pull output mode. Pull-up resistors can be assigned by software. Pins can also be assigned individually as alternative function pins. I/O port with bit-programmable pins. Configurable to input or push-pull output mode. Pull-up resistors can be assigned by software. Pins can also be assigned individually as alternative function pins. I/O port with bit-programmable pins. Configurable to input mode, push-pull output mode, or n-channel open-drain output mode. Input mode with pull-up resistors can be assigned by software. The port 2 pins have high current drive capability. Pins can also be assigned individually as alternative function pins. I/O port with bit-programmable pins. Configurable to input or push-pull output mode. Pull-up resistors can be assigned by software. Pins can also be assigned individually as alternative function pins. System clock input and output pins Test signal input pin (for factory use only; must be connected to VSS.) Power supply input pin Ground pin Circuit Type D-1 E-2 28 Pin No. 5-7 Shared Functions RxD, TxD RESETB
P1.0 - P1.1 P1.2 - P1.7
I/O
D-2 E-1
9-16 ( 11-18 / 11- 18 )
INT0-INT1 ADC0-ADC7 TDOUT
P2.0,P2.3 P2.5,P2.7 P2.1-P2.2 P2.4,P2.6
I/O
D-1 E
17-24 ( 19-23, 26-28 / 19-23, 24-26)
TAOUT/TACK TACAP TBOUT T1CAP/T1CK T1OUT PWM
P3.0-P3.2 (P3.3-P3.6)
I/O
D-1 (E)
XIN, XOUT TEST VDD VSS
I, O I - -
- _ - -
25-27 ( 29-31, 8-9, 24-25 / 27-29, 8, 23 ) 2,3 4 28 (32/30) 1
SI/SO/SCK
- _ - -
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PRODUCT OVERVIEW
Table 1-2. Pin Descriptions of 28-SOP (32-SOP,32-SDIP / 30-SDIP) Pin Names SCK SO SI PWM ADC0-7 Pin Type I/O O I O I Pin Description Serial interface clock input or output Serial data output Serial data output PWM output A/D converter analog input channels Circuit Type D-1 D-1 D-1 D-1 E-1 28 Pin No. 27(31/29) 26(30/28) 25(29/27) 24(28/26) 9-16 (11-18 / 10-17) 8(10/9) D-1 D-1 D-2 5 6 9-10 (11,12 /10,11) 17(19/18) 18(20/19) 19(21/20) 22(26/24) 21(23/22) 23(27/25) 20(22/21) 15(17/16) 7 P0.0 P0.1 P1.0 P1.1 P2.0 P2.1 P2.2 P2.5 P2.4 P2.6 P2.3 P1.6 ADC6 P0.2 Shared Functions P3.2 P3.1 P3.0 P2.7 P1.0-P1.7
AVREF RxD TxD INT0 INT1 TAOUT TACK TACAP T1OUT T1CK T1CAP TBOUT TDOUT RESETB
I I/O O I
A/D converter reference voltage Serial data RXD pin for receive input and transmit output (mode 0) Serial data TXD pin for transmit output and shift clock output (mode 0) External interrupts.
O I I O I I O O I
Timer/counter(A) match output, or Timer/counter(A) PWM output Timer/counter(A) external clock input Timer/counter(A) external capture input Timer/counter(0) match output, or Timer/counter(0) PWM output Timer/counter(0) external clock input Timer/counter(0) external capture input Timer/counter(B) match output, or Timer/counter(B) PWM output Timer/counter(B) match output, or Timer/counter(B) PWM output System reset signal input pin
D-1 E E D-1 E E D-1 D-1 B
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PRODUCT OVERVIEW
S3C9498/F9498
PIN CIRCUITS
VDD
Pull-up Enable
IN
Data Output Disable
Pin Circuit Type C
I/O
Figure 1-5. Pin Circuit Type B (nRESET)
Figure 1-6. Pin Circuit Type D-1
VDD Pull-up Enable VDD
VDD
Data
P-Channel Out
Data Output Disable Ext.INT Input Normal Noise Filter
Pin Circuit Type C
I/O
Output Disable
N-Channel
Figure 1-7. Pin Circuit Type C
Figure 1-8. Pin Circuit Type D-2
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PRODUCT OVERVIEW
VDD PNE Pull-up resistor Pull-up Enable P-CH Data Output DIsable N-CH In/Out
VDD
Schmitt Trigger
Figure 1-9. Pin Circuit Type E
VDD Pull-up Resistor Pull-up Enable
VDD PNE
Data Output Disable
I/O
Analog Input
Figure 1-9. Pin Circuit Type E-1
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PRODUCT OVERVIEW
S3C9498/F9498
VDD Pull-up register (50 kW typical) Pull-up enable
Open-drain
VDD Smart option
Data Output DIsable (input mode) Input Data MUX
MUX
In/Out
nRESET
Figure 1-11. Pin Circuit Type E-2
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ADDRESS SPACES
2
OVERVIEW
ADDRESS SPACES
The S3C9498/F9498 microcontroller has two kinds of address space: -- Internal program memory (ROM) -- Internal register file A 13-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and data between the CPU and the internal register file. The S3C9498/F9498 have 8-Kbytes of on-chip program memory, which is configured as the Internal ROM mode, all of the 8-Kbyte internal program memory is used. The S3C9498/F9498 microcontroller has 208 general-purpose registers in its internal register file. 45 bytes in the register file are mapped for system and peripheral control functions.
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ADDRESS SPACES
S3C9498/F9498
PROGRAM MEMORY (ROM)
Program memory (ROM) stores program codes or table data. The S3C9498/F9498 have 8Kbytes of internal multi time programmable (MTP) program memory (see Figure 2-1). The first 2-bytes of the ROM (0000H-0001H) are interrupt vector address. Unused locations (0002H-00FFH except 3CH, 3DH, 3EH, and 3FH) can be used as normal program memory. The location 3CH, 3DH, 3EH, and 3FH is used as smart option ROM cell. The program reset address in the ROM is 0100H.
(Decimal) 8,191
(HEX) 1FFFH
8-Kbyte Program Memory Area
0200H Program Start 0100H 003FH 003CH 0002H Interrupt Vector Area 0 0000H
Smart option ROM cell
Figure 2-1. Program Memory Address Space
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ADDRESS SPACES
Smart Option Smart option is the ROM option for starting condition of the chip. The ROM addresses used by smart option are from 003CH to 003FH. The default value of ROM is FFH.
ROM Address: 003CH MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used ROM Address: 003DH MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
ROM Address: 003EH MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
LVR enable or disable bit: 0 = Disable 1 = Enable
LVR level selection bits: 10001 = 3 V
Not used
ROM Address: 003FH MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
P0.2/nRESET pin selection bit: 0 = Nomal I/O P0.2 pin enable 1 = nRESET Pin enable
NOTES: 1. The unused bits of 3CH, 3DH, 3EH, 3FH must be logic "1". 2. When LVR is enabled, LVR level must be set to appropriate value(10001B), not default value.
Figure 2-2. Smart Option
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S3C9498/F9498
REGISTER ARCHITECTURE
The upper 64-bytes (C0H-FFH) of the S3C9498/F9498 internal register file are addressed as working registers, system control registers and peripheral control registers. The lower 192-bytes of internal register file (00H-BFH) is called the general-purpose register space. 253 registers in this space can be accessed; 208 are available for general-purpose use. For many SAM88RCRI microcontrollers, the addressable area of the internal register file is further expanded by additional register pages at space of the general purpose register (00H-BFH). This register file expansion is not implemented in the S3C9498/F9498, however. The specific register types and the area (in bytes) that they occupy in the internal register file are summarized in Table 2-1. Table 2-1. Register Type Summary Register Type System and peripheral registers General-purpose registers (including the 16-bit common working register area) Total Addressable Bytes Number of Bytes 45 208 253
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ADDRESS SPACES
FFH Peripheral Control Registers 64 Bytes of Common Area E0H DFH D0H CFH C0H BFH
System Control Registers Working Registers
192 Bytes ~
General Purpose Register File and Stack Area
00H
Figure 2-3. Internal Register File Organization
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ADDRESS SPACES
S3C9498/F9498
COMMON WORKING REGISTER AREA (C0H-CFH)
The SAM88RCRI register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. This 16-byte address range is called common area. That is, locations in this area can be used as working registers by operations that address any location on any page in the register file. Registers are addressed either as a single 8-bit register or as a paired 16-bit register. In 16-bit register pairs, the address of the first 8-bit register is always an even number and the address of the next register is an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register; the least significant byte is always stored in the next (+ 1) odd-numbered register.
MSB Rn
LSB Rn+1
n = Even address
Figure 2-4. 16-Bit Register Pairs
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ADDRESS SPACES
SYSTEM STACK
S3F9-series microcontrollers use the system stack for subroutine calls and returns and to store data. The PUSH and POP instructions are used to control system stack operations. The S3C9498/F9498 architecture supports stack operations in the internal register file. Stack Operations Return addresses for procedure calls and interrupts and data are stored on the stack. The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents of the PC and the FLAGS registers are pushed to the stack. The IRET instruction then pops these values back to their original locations. The stack address always decrements before a push operation and increments after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top of the stack, as shown in Figure 2-5.
High Address
PCL PCL Top of stack PCH PCH Top of stack Flags Stack contents after an interrupt
Stack contents after a call instruction
Low Address
Figure 2-5. Stack Operations Stack Pointer (SP) Register location D9H contains the 8-bit stack pointer (SP) that is used for system stack operations. After a reset, the SP value is undetermined. Because only internal memory space is implemented in the S3C9498/F9498, the SP must be initialized to an 8-bit value in the range 00H-0C0H. NOTE In case a Stack Pointer is initialized to 00H, it is decreased to FFH when stack operation starts. This means that a Stack Pointer access invalid stack area. We recommend that a stack pointer is initialized to C0H to set upper address of stack to BFH.
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ADDRESS SPACES
S3C9498/F9498
F PROGRAMMING TIP -- Standard Stack Operations Using PUSH and POP
The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: LD
* * *
SP,#0C0H
; SP C0H (Normally, the SP is set to C0H by the ; initialization routine)
PUSH PUSH PUSH PUSH
* * *
SYM R15 20H R3
; ; ; ;
Stack address 0BFH Stack address 0BEH Stack address 0BDH Stack address 0BCH

SYM R15 20H R3
POP POP POP POP
R3 20H R15 SYM
; ; ; ;
R3 Stack address 0BCH 20H Stack address 0BDH R15 Stack address 0BEH SYM Stack address 0BFH
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ADDRESSING MODES
3
OVERVIEW
-- Register (R)
ADDRESSING MODES
Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand. The operands specified in SAM88RCRI instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory. The SAM88RCRI instruction set supports seven explicit addressing modes. Not all of these addressing modes are available for each instruction. The six addressing modes and their symbols are:
-- Indirect Register (IR) -- Indexed (X) -- Direct Address (DA) -- Relative Address (RA) -- Immediate (IM)
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ADDRESSING MODES
S3C9498/F9498
REGISTER ADDRESSING MODE (R)
In Register addressing mode (R), the operand value is the content of a specified register or register pair (see Figure 3-1). Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that space (see Figure 3-2).
P rogram M e m o ry 8-bit Register File Address One-Opera n d Instruction (Exam p l e )
RegisterFi l e
d st OPCODE
Point to One Register in Register File Value use d i n Instruction Execution
OPERAND
Sam p l e Instruction: DEC CNT R ; Where CNTR is the label of an 8-bit register addre ss
Figure 3-1. Register Addressing
Register File MSB Point to RP0 ot RP1
RP0 or RP1 Selected RP points to start of working register block OPERAND
Program Memory 4-bit Working Register 3 LSBs Point to the Working Register (1 of 8)
dst
src
OPCODE Two-Operand Instruction (Example) Sample Instruction: ADD R1, R2 ;
Where R1 and R2 are registers in the currently selected working register area.
Figure 3-2. Working Register Addressing
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ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (IR)
In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6). You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to indirectly address another memory location.
Program Memory 8-bit Register File Address
Register File
dst OPCODE
ADDRESS Point to One Register in Register File Address of Operand used by Instruction
One-Operand Instruction (Example)
Value used in Instruction Execution
OPERAND
Sample Instruction: RL @SHIFT ; Where SHIFT is the label of an 8-bit register address
Figure 3-3. Indirect Register Addressing to Register File
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ADDRESSING MODES
S3C9498/F9498
INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File
Program Memory Example Instruction References Program Memory REGISTER PAIR Points to Register Pair 16-Bit Address Points to Program Memory
dst OPCODE
Program Memory Sample Instructions: CALL JP @RR2 @RR2
Value used in Instruction
OPERAND
Figure 3-4. Indirect Register Addressing to Program Memory
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ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points to start fo working register block
Program Memory 4-bit Working Register Address 3 LSBs Point to the Working Register (1 of 8)
~
~
dst
src
OPCODE
ADDRESS
~
Sample Instruction: OR R3, @R6 Value used in Instruction OPERAND
~
Figure 3-5. Indirect Working Register Addressing to Register File
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ADDRESSING MODES
S3C9498/F9498
INDIRECT REGISTER ADDRESSING MODE (Concluded)
Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points to start of working register block Next 2-bit Point to Working Register Pair (1 of 4) LSB Selects Register Pair 16-Bit address points to program memory or data memory
Program Memory 4-bit Working Register Address dst src OPCODE
Example Instruction References either Program Memory or Data Memory
Program Memory or Data Memory
Value used in Instruction
OPERAND
Sample Instructions: LCD LDE LDE R5,@RR6 R3,@RR14 @RR4, R8 ; Program memory access ; External data memory access ; External data memory access
Figure 3-6. Indirect Working Register Addressing to Program or Data Memory
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ADDRESSING MODES
INDEXED ADDRESSING MODE (X)
Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory. In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range -128 to +127. This applies to external memory accesses only (see Figure 3-8.) For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained in a working register. For external memory accesses, the base address is stored in the working register pair designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to that base address (see Figure 3-9). The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction (LD). The LDC and LDE instructions support Indexed addressing mode for internal program memory and for external data memory, when implemented.
Register File
RP0 or RP1
~
Value used in Instruction OPERAND
~
Selected RP points to start of working register block
+
Program Memory Two-Operand Instruction Example Base Address dst/src x OPCODE 3 LSBs Point to One of the Woking Register (1 of 8)
~
INDEX
~
Sample Instruction: LD R0, #BASE[R1] ; Where BASE is an 8-bit immediate value
Figure 3-7. Indexed Addressing to Register File
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ADDRESSING MODES
S3C9498/F9498
INDEXED ADDRESSING MODE (Continued)
Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points to start of working register block
~
Program Memory 4-bit Working Register Address OFFSET dst/src x OPCODE NEXT 2 Bits Point to Working Register Pair (1 of 4) Register Pair
~
LSB Selects
+
8-Bits 16-Bits
Program Memory or Data Memory
16-Bit address added to offset
16-Bits Sample Instructions: LDC LDE R4, #04H[RR2] R4,#04H[RR2]
OPERAND
Value used in Instruction
; The values in the program address (RR2 + 04H) are loaded into register R4. ; Identical operation to LDC example, except that external program memory is accessed.
Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset
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ADDRESSING MODES
INDEXED ADDRESSING MODE (Concluded)
Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points to start of working register block
Program Memory OFFSET 4-bit Working Register Address OFFSET dst/src src OPCODE NEXT 2 Bits Point to Working Register Pair
~
~
Register Pair 16-Bit address added to offset
LSB Selects
+
8-Bits 16-Bits
Program Memory or Data Memory
16-Bits Sample Instructions: LDC LDE R4, #1000H[RR2] R4,#1000H[RR2]
OPERAND
Value used in Instruction
; The values in the program address (RR2 + 1000H) are loaded into register R4. ; Identical operation to LDC example, except that external program memory is accessed.
Figure 3-9. Indexed Addressing to Program or Data Memory
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ADDRESSING MODES
S3C9498/F9498
DIRECT ADDRESS MODE (DA)
In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed. The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory (LDC) or to external data memory (LDE), if implemented.
Program or Data Memory
Program Memory
Memory Address Used
Upper Address Byte Lower Address Byte dst/src "0" or "1" OPCODE
LSB Selects Program Memory or Data Memory: "0" = Program Memory "1" = Data Memory
Sample Instructions: LDC LDE R5,1234H R5,1234H ; ; The values in the program address (1234H) are loaded into register R5. Identical operation to LDC example, except that external program memory is accessed.
Figure 3-10. Direct Addressing for Load Instructions
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ADDRESSING MODES
DIRECT ADDRESS MODE (Continued)
Program Memory
Next OPCODE
Memory Address Used Upper Address Byte Lower Address Byte OPCODE
Sample Instructions: JP CALL C,JOB1 DISPLAY ; ; Where JOB1 is a 16-bit immediate address Where DISPLAY is a 16-bit immediate address
Figure 3-11. Direct Addressing for Call and Jump Instructions
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ADDRESSING MODES
S3C9498/F9498
RELATIVE ADDRESS MODE (RA)
In Relative Address (RA) mode, a twos-complement signed displacement between - 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately following the current instruction. The instructions that support RA addressing is JR.
Program Memory
Next OPCODE Program Memory Address Used
Current Instruction
Displacement OPCODE
Current PC Value Signed Displacement Value
+
Sample Instructions: JR ULT,$+OFFSET ; Where OFFSET is a value in the range +127 to -128
Figure 3-12. Relative Addressing
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ADDRESSING MODES
IMMEDIATE MODE (IM)
In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. Immediate addressing mode is useful for loading constant values into registers.
Program Memory OPERAND OPCODE
(The Operand value is in the instruction) Sample Instruction: LD R0,#0AAH
Figure 3-13. Immediate Addressing
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S3C9498/F9498
NOTES
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CONTROL REGISTER
4
OVERVIEW
CONTROL REGISTERS
Control register descriptions are arranged in alphabetical order according to register mnemonic. More detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in Part II of this manual. The locations and read/write characteristics of all mapped registers in the S3C9498/F9498 register file are listed in Table 4-1. The hardware reset value for each mapped register is described in Chapter 8, "RESET and Power-Down." Ta ble 4-1. System and Peripheral Registers Register Name Timer C control register Timer D control register Timer C data register register Timer D data register register System Clock control register System flags register UART Baud rate data register STOP control register Timer Counter selection register Stack pointer register Timer counter register Mnemonic TCCON TDCON TCDATA TDDATA CLKCON FLAGS BRDATA STPCON TCNTSEL SP TCNT Location DBH is not mapped Basic timer control register Basic timer counter register BTCON BTCNT Location DEH is not mapped System mode register SYM 223 DFH R/W 220 221 DCH DDH R/W R Decimal 208 209 210 211 212 213 214 215 216 217 218 Hex D0H D1H D2H D3H D4H D5H D6H D7H D8H D9H DAH R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
4-1
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CONTROL REGISTERS
S3C9498/F9498
Table 4-1. System and Peripheral Registers (continued) Register Name Port 0 Data Register Port 1 Data Register Port 2 Data Register Port 3 Data Register PWM data register PWM extension data register Port 0 control register P1 interrupt control register Port 1 control High register Port 1 control Low register Port 2 control High register Port 2 control Low register Port 3 control register PWM control register Timer 1 data register(high byte) Tim er 1 data register(low byte) Timer 1 control register Serial I/O control register Timer Interrupt pending register Timer A control register SIO pre-scalar register Timer A data register Timer B data register Mnemonic P0 P1 P2 P3 PWMDATA PWMEX P0CON P1INT P1CONH P1CONL P2CONH P2CONL P3CON PWMCON T1DATAH T1DATAL T1CON SIOCON TINTPND TACON SIOPS TADATA TBDATA Location F7H is not mapped Timer B control register SIO data register A/D converter data register(high byte) A/D converter data register(low byte) A/D converter control register UART control register UART pending register UART data register TBCON SIODATA ADDATAH ADDATAL ADCON UARTCON UARTPND UDATA 248 249 250 251 252 253 254 255 F8H F9H FAH FBH FCH FDH FEH FFH R/W R/W R R R/W R/W R/W R/W Decimal 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 Hex E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH EBH ECH EDH EEH EFH F0H F1H F2H F3H F4H F5H F6H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
4-2
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S3C9498/F9498
CONTROL REGISTER
Bit number(s) that is/are appended to the register name for bit addressing Register ID Register name
Name of individual bit or related bits Register address (hexadecimal)
Register location in the internal register file
FLAGS - System Flags Register
.7 .6 .5 .4 .3 x R/W
D5H
.2 x R/W .1 0 R
Set 1
.0 0 R/W
Bit Identifier RESET Value Read/Write Bit Addressing Mode .7
x x x x R/W R/W R/W R/W Register addressing mode only
Carry Flag (C) 0 0 Operation does not generate a carry or borrow condition Operation generates carry-out or borrow into high-order bit 7
.6
Zero Flag (Z) 0 0 Operation result is a non-zero value Operation result is zero
.5
Sign Flag (S) 0 0 Operation generates positive number (MSB = "0") Operation generates negative number (MSB = "1")
R = Read-only W = Write-only R/W = Read/write '-' = Not used Type of addressing that must be used to address the bit (1-bit, 4-bit, or 8-bit)
Description of the effect of specific bit settings
RESETvalue notation: '-' = Not used 'x' = Undetermined value '0' = Logic zero '1' = Logic one
Bit number: MSB = Bit 7 LSB = Bit 0
Figure 4-1. Register Description Format
4-3
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CONTROL REGISTERS
S3C9498/F9498
ADCON -- A/D Converter Control Register
Bit Identifier RESET Value Read/Write .7-.4 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W
FCH
.0 0 R/W
A/D Input Pin Selection Bits 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 Connected with GND internally
Other value
.3
End-Of-Conversion (EOC) Status Bit 0 1 A/D conversion is in progress A/D conversion complete
.2-.1
Clock Source Selection Bits 0 0 1 1 0 1 0 1 fxx/16 (OSC 8MHz) fxx/8 (OSC 8MHz) fxx/4 (OSC 8MHz) Fxx (fOSC 2.5MHz)
.0
A/D Conversion Start Bit 0 1 Disable operation Start operation
NOTE:
Maximum ADC clock input = 4MHz.
4-4
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S3C9498/F9498
CONTROL REGISTER
BTCON -- Basic Timer Control Register
Bit Identifier RESET Value Read/Write .7-.4 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W
DCH
.0 0 R/W
Watchdog Timer Function Enable Bit 1 0 1 0 Disable watchdog timer function Enable watchdog timer function
Others
.3-.2
Basic Timer Input Clock Selection Code 0 0 1 1 0 1 0 1 fOSC/4096 fOSC/1024 fOSC/128 Invalid setting
.1
Basic Timer 8-Bit Counter Clear Bit 0 1 No effect Clear the basic timer counter value
.0
Basic Timer Divider Clear Bit 0 1 No effect Clear both dividers
NOTE:
When you write a "1" to BTCON.0 (or BTCON.1), the basic timer counter (or basic timer divider) is cleared. The bit is then cleared automatically to "0".
4-5
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CONTROL REGISTERS
S3C9498/F9498
CLKCON -- System Clock Control Register
Bit Identifier RESET Value Read/Write .7 .7 0 R/W .6 - - .5 - - .4 0 R/W .3 0 R/W .2 - - .1 - -
D4H
.0 - -
Oscillator IRQ Wake-up Function Enable Bit 0 1 Enable IRQ for main system oscillator wake-up function Disable IRQ for main system oscillator wake-up function
.6-.5
Not used for the S3C9498/F9498
.4-.3
CPU Clock (System Clock) Selection Bits (note) 0 0 1 1 0 1 0 1 fxx/16 fxx/8 fxx/2 fxx/1 (non-divided)
.2-.0
NOTE:
Not used for the S3C9498/F9498
After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster clock speeds, load the appropriate values to CLKCON.3 and CLKCON.4.
4-6
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S3C9498/F9498
CONTROL REGISTER
FLAGS -- System Flags Register
Bit Identifier RESET Value Read/Write .7 .7 x R/W .6 x R/W .5 x R/W .4 x R/W .3 - - .2 - - .1 - -
D5H
.0 - -
Carry Flag (C) 0 1 Operation does not generate a carry or borrow condition Operation generates a carry-out or borrow into high-order bit 7
.6
Zero Flag (Z) 0 1 Operation result is a non-zero value Operation result is zero
.5
Sign Flag (S) 0 1 Operation generates a positive number (MSB = "0") Operation generates a negative number (MSB = "1")
.4
Overflow Flag (V) 0 1 Operation result is + 127 or _ - 128 Operation result is > + 127 or < - 128
.3-.0
Not used for the S3C9498/F9498
4-7
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CONTROL REGISTERS
S3C9498/F9498
P0CON -- Port 0 Control Register
Bit Identifier RESET Value Read/Write .7 - - .6 - - .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W
E6H
.0 0 R/W
.7-.6
Not used for S3C9498/F9498
.5-.4
P0.2 0 0 1 1 0 1 0 1 Input mode with pull-up Input mode, Push-pull output Open-drain Output
.3-.2
P0.1/TxD 0 0 1 1 0 1 0 1 Input mode with pull-up Input mode Push-pull output Alternative function, TxD output
.1-.0
P0.0/RxD 0 0 1 1 0 1 0 1 Input mode with pull-up; RxD input Input mode; RxD input Push-pull output Alternative function; RxD output
NOTE:
When users use Port 0, users must be care of the pull-up resistance status.
4-8
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S3C9498/F9498
CONTROL REGISTER
P1CONH -- Port 1 Control Register (High Byte)
Bit Identifier RESET Value Read/Write .7-.6 .7 0 R/W P1.7/ADC7 0 0 1 1 0 1 0 1 Input mode with pull-up Not used for S3C9498/F9498 Push-pull output Alternative function; ADC7 input .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W
E8H
.0 0 R/W
.5-.4
P1.6/ADC6/TDOUT 0 0 1 1 0 1 0 1 Input mode with pull-up Alternative function; TDOUT output Push-pull output Alternative function; ADC6 input
.3-.2
P1.5/ADC5 0 0 1 1 0 1 0 1 Input mode with pull-up Input mode Push-pull output Alternative function; ADC5 input
.1-.0
P1.4/ADC4 0 0 1 1 0 1 0 1 Input mode with pull-up Input mode Push-pull output Alternative function; ADC4 input
4-9
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CONTROL REGISTERS
S3C9498/F9498
P1CONL
Bit Identifier RESET Value Read/Write .7-.6
-- Port 1 Control Register (Low Byte)
.7 0 R/W P1.3/ADC3 0 0 1 1 0 1 0 1 Input mode with pull-up Input mode Push-pull output Alternative function; ADC3 input .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W
E9H
.0 0 R/W
.5-.4
P1.2/ADC2 0 0 1 1 0 1 0 1 Input mode with pull-up Input mode Push-pull output Alternative function; ADC2 input
.3-.2
P1.1/ADC1/INT1 0 0 1 1 0 1 0 1 Input mode with pull-up; INT1 input Input mode; INT1 input Push-pull output Alternative function; ADC1 input
.1-.0
P1.0/ADC0/INT0 0 0 1 1 0 1 0 1 Input mode with pull-up; INT0 input Input mode; INT0 input Push-pull output Alternative function; ADC0 input
4-10
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S3C9498/F9498
CONTROL REGISTER
P1INT
-- Port 1 Interrupt Control Register
.7 - - .6 - - .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W
E7H
.0 0 R/W
Bit Identifier RESET Value Read/Write
.7-.6
Not used for S3C9498/F9498
.5-.4
P1.1/ INT1 Interrupt Enable/Disable Selection Bits 0 1 1 X 0 1 Interrupt Disable Interrupt Enable; falling edge Interrupt Enable; rising edge
.3-.2
P1.0/ INT0 Interrupt Enable/Disable Selection Bits 0 1 1 X 0 1 Interrupt Disable Interrupt Enable; falling edge Interrupt Enable; rising edge
.1
INT1 Interrupt Pending Bit 0 1 No interrupt pending (Clear pending bit when write) Interrupt pending
.0
INT0 Interrupt Pending Bit 0 1 No interrupt pending (Clear pending bit when write) Interrupt pending
4-11
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CONTROL REGISTERS
S3C9498/F9498
P2CONH -- Port 2 Control Register (High Byte)
Bit Identifier RESET Value Read/Write .7-.6 .7 0 R/W P2.7/PWM 0 0 1 1 0 1 0 1 Input mode with pull-up Input mode Push-pull output Alternative function; PWM signal output .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W
EAH
.0 0 R/W
.5-.4
P2.6/T1CAP 0 0 1 1 0 1 0 1 Input mode with pull-up; T1CAP input Input mode; T1CAP input Push-pull output Open-drain output
.3-.2
P2.5/T1OUT 0 0 1 1 0 1 0 1 Input mode with pull-up Input mode Push-pull output Alternative function; T1OUT signal output
.1-.0
P2.4/T1CK 0 0 1 1 0 1 0 1 Input mode with pull-up; T1CK input Input mode; T1CK input Push-pull output Open-drain output
4-12
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S3C9498/F9498
CONTROL REGISTER
P2CONL -- Port 2 Control Register (Low Byte)
Bit Identifier RESET Value Read/Write .7-.6 .7 0 R/W P2.3/TBOUT 0 0 1 1 0 1 0 1 Input mode with pull-up Input mode Push-pull output Alternative function; TBOUT signal output .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W
EBH
.0 0 R/W
.5-.4
P2.2/TACAP 0 0 1 1 0 1 0 1 Input mode with pull-up; TACAP input Input mode; TACAP input Push-pull output Open-drain output
.3-.2
P2.1/TACK 0 0 1 1 0 1 0 1 Input mode with pull-up; TACK input Input mode; TACK input Push-pull output Open-drain output
.1-.0
P2.0/TAOUT 0 0 1 1 0 1 0 1 Input mode with pull-up Input mode Push-pull output Alternative function; TAOUT signal output
4-13
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CONTROL REGISTERS
S3C9498/F9498
P3CON -- Port 3 Control Register
Bit Identifier RESET Value Read/Write .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W
ECH
.0 0 R/W
P3.6/P3.5/P3.4/P3.3 0 0 1 1 0 1 0 1 Input mode with pull-up Input mode Push-pull output Open-drain output
.5-.4
P3.2/SCK 0 0 1 1 0 1 0 1 Input mode, pull-up (SCK input) Input mode (SCK input) Push-pull output Alternative output mode (SCK output)
.3-.2
P3.1/SO 0 0 1 1 0 1 0 1 Input mode, pull-up Input mode Push-pull output Alternative output mode (SO)
.1-.0
P3.0/SI 0 0 1 1 0 1 0 1 Input mode(SI) , pull-up Input mode (SI) Push-pull output Alternative output mode(Not used)
4-14
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S3C9498/F9498
CONTROL REGISTER
PWMCON -- PWM Control Register
Bit Identifier RESET Value Read/Write .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W
EDH
.0 0 R/W
PWM Input Clock Selection Bit 0 0 1 1 0 1 0 1 fosc/256 fosc/64 fosc/8 fosc/1
.5
PWM Data Reload Interval Selection Bit 0 1 Reload from 12-bit up counter overflow Reload from 6-bit up counter overflow
.4 .3
Not used for S3C9498/F9498 PWM Counter Clear Bit 0 1 No effect Clear 12-bit up counter (when write)
.2
PWM Counter Enable Bit 0 1 Stop counter Start (Resume counting)
.1
PWM Overflow Interrupt Enable bit (12-bit Counter Overflow) 0 1 Disable interrupt Enable interrupt
.0
PWM 12-Bit Counter Overflow Interrupt Pending Bit 0 0 1 No interrupt pending Clear pending condition (when write) Interrupt pending (Clear pending bit when write)
4-15
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CONTROL REGISTERS
S3C9498/F9498
SIOCON -- Serial I/O Module Control Registers
Bit Identifier RESET Value Read/Write .7 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W
F1H
.0 0 R/W
SIO Shift Clock Selection Bit 0 1 Interval clock (P.S Clock) External clock (SCK)
.6
Data Direction Control Bit 0 1 MSB-first mode LSB-first mode
.5
SIO Mode Selection Bit 0 1 Receive-only mode Transmit/Receive mode
.4
Shift Clock Edge Selection Bit 0 1 Tx at falling edges, Rx at rising edges. Tx at rising edges, Rx at falling edges.
.3
SIO Counter Clear and Shift Start Bit 0 1 No action Clear 3-bit counter and start shifting
.2
SIO Shift Operation Enable Bit 0 1 Disable shift and clock counter Enable shift and clock counter
.1
SIO Interrupt Enable Bit 0 1 Disable SIO interrupt Enable SIO interrupt
.0
SIO Interrupt Pending Bit 0 1 No interrupt pending Interrupt pending (Clear pending bit when write)
4-16
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S3C9498/F9498
CONTROL REGISTER
SP -- Stack Pointer
Bit Identifier RESET Value Read/Write .7-.0 .7 x R/W .6 x R/W .5 x R/W .4 x R/W .3 x R/W .2 x R/W .1 x R/W
D9H
.0 X R/W
Stack Pointer Address The stack pointer value is 8-bit stack pointer address (SP7-SP0). The SP value is undefined following a reset.
STPCON -- Stop Control Register
Bit Identifier RESET Value Read/Write .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W
D7H
.0 0 R/W
.7-.0
STOP Control Bits 10100101 Other values Enable stop instruction Disable stop instruction
NOTE:
Before executing the STOP instruction, you must set this STPCON register as "10100101b". Otherwise the STOP instruction will not be executed.
4-17
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CONTROL REGISTERS
S3C9498/F9498
SYM -- System Mode Register
Bit Identifier RESET Value Read/Write .7 - - .6 - - .5 - - .4 - - .3 0 R/W .2 0 R/W .1 0 R/W
DFH
.0 0 R/W
.7-.4
Not used for S3C9498/F9498
.3
Global Interrupt Enable Bit 0 1 Disable all interrupts Enable all interrupt
.2-.0
Page Select Bits 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Page 0 Page 1 (Not used for S3C9498/F9498) Page 2 (Not used for S3C9498/F9498) Page 3 (Not used for S3C9498/F9498) Page 4 (Not used for S3C9498/F9498) Page 5 (Not used for S3C9498/F9498) Page 6 (Not used for S3C9498/F9498) Page 7 (Not used for S3C9498/F9498)
NOTE:
Following a reset, you must enable global interrupt processing by executing an EI instruction (not by writing a "1" to SYM.3).
4-18
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S3C9498/F9498
CONTROL REGISTER
T1CON -- Timer 1 Control Register
Bit Identifier RESET Value Read/Write Addressing Mode .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W
F0H
.0 0 R/W
Register addressing mode only
.7-.5
Timer 1 Input Clock Selection Bits 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fxx/1024 fxx (Non-divide) fxx/256 External clock falling edge fxx/64 External clock rising edge fxx/8 Counter stop
.4-.3
Timer 1 Operating Mode Selection Bits 0 0 1 1 0 1 0 1 Interval mode Capture mode (Capture on rising edge, OVF can occur) Capture mode (Capture on falling edge, OVF can occur) PWM mode
.2
Timer 1 Counter Clear Bit 0 1 No effect Clear the timer 1 counter (Auto-clear bit)
.1
Timer 1 Match/Capture Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
.0
Timer 1 Overflow Interrupt Enable 0 1 Disable overflow interrupt Enable overflow interrupt
4-19
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CONTROL REGISTERS
S3C9498/F9498
TACON -- Timer A Control Register
Bit Identifier RESET Value Read/Write .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W
F3H
.0 0 R/W
Timer A Input Clock Selection Bits 0 0 1 1 0 1 0 1 fxx/1024 fxx/256 fxx/64 External clock (TACK)
.5-.4
Timer A Operating Mode Selection Bits 0 0 1 1 0 1 0 1 Internal mode (TAOUT mode) Capture mode (capture on rising edge, counter running, OVF can occur) Capture mode (capture on falling edge, counter running, OVF can occur) PWM mode (OVF interrupt can occur)
.3
Timer A Counter Clear Bit 0 1 No effect Clear the timer A counter (After clearing, return to zero)
.2
Timer A Overflow Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
.1
Timer A Match/Capture Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
.0
Timer A Start/Stop Bit 0 1 Stop Timer A Start Timer A
4-20
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S3C9498/F9498
CONTROL REGISTER
TBCON -- Timer B Control Register
Bit Identifier RESET Value Read/Write .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 - - .3 0 R/W .2 0 R/W .1 0 R/W
F8H
.0 0 R/W
Timer B Input Clock Selection Bits 0 0 1 1 0 1 0 1 fxx/8 fxx/4 fxx/2 fxx/1
.5
Not used for S3C9498/F9498
.4
Timer B Operating Mode Selection Bits 0 1 Interval mode (TBOUT mode) PWM mode (OVF interrupt can occur)
.3
Timer B Counter Clear Bit 0 1 No effect Clear the timer B counter (After clearing, return to zero)
.2
Timer B Overflow Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
.1
Timer B Match Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
.0
Timer B Start/Stop Bit 0 1 Stop Timer B Start Timer B
4-21
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CONTROL REGISTERS
S3C9498/F9498
TCCON -- Timer C Control Register
Bit Identifier RESET Value Read/Write .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W
D0H
.0 0 R/W
.7
Timer 0 operation mode selection bit 0 1 Two 8-bit timers mode (Timer C/D) One 16-bit timer mode (Timer 0)
.6
Not used for S3C9498/F9498 (Must be kept `0')
.5-.4
Timer C Input Clock Selection Bits 0 0 1 1 0 1 0 1 Fxx/1024 fxx/512 fxx/8 fxx
.3
Timer C Counter Clear Bit 0 1 No affect Clear the timer C counter (when write)
.2
Timer C Counter Run Enable Bit 0 1 Disable counter running Enable counter running
.1
Timer C Interrupt Enable Bit 0 1 Disable Interrupt Enable Interrupt
.0
Timer C Interrupt pending Bit 0 1 No interrupt pending (Clear pending bit when write) Interrupt pending
4-22
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S3C9498/F9498
CONTROL REGISTER
TCNTSEL -- Timer Counter read selection Register
Bit Identifier RESET Value Read/Write .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W
D8H
.0 0 R/W
.7-.3
Not used for S3C9498/F9498
.2-.0
Timer counter read selection bits 0 0 0 0 1 1 0 0 1 1 X X 0 1 0 1 0 1 Select Timer A counter Select Timer B counter Select Timer C counter Select Timer D counter Select Timer 1 counter high byte Select Timer 1 counter low byte
4-23
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CONTROL REGISTERS
S3C9498/F9498
TDCON -- Timer D Control Register
Bit Identifier RESET Value Read/Write Addressing Mode .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W
D1H
.0 0 R/W
Register addressing mode only
.7-.6
Timer D operating Mode Selection Bits 0 0 1 1 0 1 0 1 Interval mode 6-bit PWM mode (OVF interrupt can occur) 7-bit PWM mode (OVF interrupt can occur) 8-bit PWM mode (OVF interrupt can occur)
.5-.4
Timer D Clock Selection Bits 0 0 1 1 0 1 0 1 fxx/8 fxx/4 fxx/2 fxx
.3
Timer D Counter Clear Bit 0 1 No effect Clear the timer D counter (when write)
.2
Timer D Count Enable Bit 0 1 Disable count operation Enable count operation
.1
Timer D match Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
.0
Timer D overflow interrupt enable bit 0 1 Disable interrupt Enable interrupt
4-24
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S3C9498/F9498
CONTROL REGISTER
TINTPND -- Interrupt Pending Register
Bit Identifier RESET Value Read/Write .7 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W
F2H
.0 0 R/W
Timer 1 Overflow Interrupt Pending Bit 0 No interrupt pending (Clear pending bit when write) 1 Interrupt pending
.6
Timer 1 Match/Capture Interrupt Pending Bit 0 1 No interrupt pending (Clear pending bit when write) Interrupt pending
.5
Timer D Overflow Interrupt Pending Bit 0 1 No interrupt pending (Clear pending bit when write) Interrupt pending
.4
Timer D Match Interrupt Pending Bit 0 1 No interrupt pending (Clear pending bit when write) Interrupt pending
.3
Timer B Overflow Interrupt Pending Bit 0 1 No interrupt pending (Clear pending bit when write) Interrupt pending
.2
Timer B Match/Capture Interrupt Pending Bit 0 1 No interrupt pending (Clear pending bit when write) Interrupt pending
.1
Timer A Overflow Interrupt Pending Bit 0 1 No interrupt pending (Clear pending bit when write) Interrupt pending
.0
Timer A Match/Capture Interrupt Pending Bit 0 1 No interrupt pending (Clear pending bit when write) Interrupt pending
4-25
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CONTROL REGISTERS
S3C9498/F9498
UARTCON -- UART Control Register
Bit Identifier RESET Value Read/Write Addressing Mode .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W
FDH
.0 0 R/W
Register addressing mode only
.7-.6
Operating mode and baud rate selection bits 0 0
1
0 1
0
Mode 0: SIO mode [fxx/(16 x (BRDATA1 + 1))] Mode 1: 8-bit UART [fxx/(16 x (BRDATA1 + 1))] Mode 2: 9-bit UART [fxx/16] Mode 3: 9-bit UART [fxx/(16 x (BRDATA1 + 1))]
1
1
.5
Multiprocessor communication (1) enable bit (for modes 2 and 3 only) 0 1 Disable Enable
.4
Serial data receive enable bit 0 1 Disable Enable
.3
Location of the 9th data bit to be transmitted in UART mode 2 or 3 ("0" or "1")
.2
Location of the 9th data bit that was received in UART mode 2 or 3 ("0" or "1")
.1
Receive interrupt enable bit 0 1 Disable Receive interrupt Enable Receive interrupt
.0
Transmit interrupt enable bit 0 1 Disable Transmit interrupt Enable Transmit Interrupt
NOTES: 1. In mode 2 or 3, if the MCE (UARTCON.5) bit is set to "1", then the receive interrupt will not be activated if the received 9th data bit is "0". In mode 1, if MCE = "1", then the receive interrupt will not be activated if a valid stop bit was not received. In mode 0, the MCE(UARTCON.5) bit should be "0". The descriptions for 8-bit and 9-bit UART mode do not include start and stop bits for serial data receive and transmit.
2.
4-26
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S3C9498/F9498
CONTROL REGISTER
UARTPND -- UART Pending and parity control
Bit Identifier RESET Value Read/Write .7 - - .6 - - .5 - - .4 - - .3 - - .2 - - .1 0 R/W
FEH
.0 0 R/W
.7-.3
Not used for the S3C9498/F9498
.1
UART receive interrupt pending flag 0 0 1 Not pending Clear pending bit (when write) Interrupt pending
.0
UART transmit interrupt pending flag 0 0 1 Not pending Clear pending bit (when write) Interrupt pending
NOTES: 1. In order to clear a data transmit or receive interrupt pending flag, you must write a "0" to the appropriate pending bit. 2. To avoid programming errors, we recommend using load instruction (except for LDB), when manipulating UARTPND values.
4-27
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CONTROL REGISTERS
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NOTES
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INTERRUPT STRUCTURE
5
OVERVIEW
INTERRUPT STRUCTURE
The SAM88RCRI interrupt structure has two basic components: a vector, and sources. The number of interrupt sources can be serviced through an interrupt vector which is assigned in ROM address 0000H.
VECTOR
SOURCES S1
0000H 0001H
S2 S3 Sn
NOTES: 1. The SAM88RCRI interrupt has only one vector address (0000H-0001H). 2. The numbern of Sn value is expandable.
Figure 5-1. S3C9-Series Interrupt Type
INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can be controlled in two ways: either globally or specific interrupt level and source. The system-level control points in the interrupt structure are therefore: -- Global interrupt enable and disable (by EI and DI instructions) -- Interrupt source enable and disable settings in the corresponding peripheral control register(s)
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INTERRUPT STRUCTURE
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ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI) The system mode register, SYM (DFH), is used to enable and disable interrupt processing. SYM.3 is the enable and disable bit for global interrupt processing respectively, by modifying SYM.3. An Enable Interrupt (EI) instruction must be included in the initialization routine that follows a reset operation in order to enable interrupt processing. Although you can manipulate SYM.3 directly to enable and disable interrupts during normal operation, we recommend that you use the EI and DI instructions for this purpose. INTERRUPT PENDING FUNCTION TYPES When the interrupt service routine has executed, the application program's service routine must clear the appropriate pending bit before the return from interrupt subroutine (IRET) occurs. INTERRUPT PRIORITY Because there is not a interrupt priority register in SAM88RCRI, the order of service is determined by a sequence of source which is executed in interrupt service routine.
"EI" Instruction Execution RESET Source Interrupts Source Interrupt Enable
S R
Q
Interrupt Pending Register Interrpt priority is determind by software polling method
Vector Interrupt Cycle
Global Interrupt Control (EI, DI instruction)
Figure 5-2. Interrupt Function Diagram
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INTERRUPT STRUCTURE
INTERRUPT SOURCE SERVICE SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request pending bit to "1". 2. The CPU generates an interrupt acknowledge signal. 3. The service routine starts and the source's pending flag is cleared to "0" by software. 4. Interrupt priority must be determined by software polling method.
INTERRUPT SERVICE ROUTINES Before an interrupt request can be serviced, the following conditions must be met: -- Interrupt processing must be enabled (EI, SYM.3 = "1") -- Interrupt must be enabled at the interrupt's source (peripheral control register) If all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. The CPU then initiates an interrupt machine cycle that completes the following processing sequence: 1. Reset (clear to "0") the global interrupt enable bit in the SYM register (DI, SYM.3 = "0") to disable all subsequent interrupts. 2. Save the program counter and status flags to stack. 3. Branch to the interrupt vector to fetch the service routine's address. 4. Pass control to the interrupt service routine. When the interrupt service routine is completed, an Interrupt Return instruction (IRET) occurs. The IRET restores the PC and status flags and sets SYM.3 to "1" (EI), allowing the CPU to process the next interrupt request. GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM contains the address of the interrupt service routine. Vectored interrupt processing follows this sequence: 1. Push the program counter's low-byte value to stack. 2. Push the program counter's high-byte value to stack. 3. Push the FLAGS register values to stack. 4. Fetch the service routine's high-byte address from the vector address 0000H. 5. Fetch the service routine's low-byte address from the vector address 0001H. 6. Branch to the service routine specified by the 16-bit vector address.
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INTERRUPT STRUCTURE
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S3C9498/F9498 INTERRUPT STRUCTURE The S3F9498 microcontroller has four peripheral interrupt sources: -- Timer A/ B match / overflow, Timer C / D interrupt, Timer 1 match / overflow interrupt -- UART transmit interrupt / receive interrupt, PWM overflow interrupt -- SIO interrupt, INT0, INT1 external interrupt
Vector
Pending Bits TINTPND.0
Enable/Disable
Source Timer A Match
TACON.1 TINTPND.1 Timer A Overflow TACON.2 Timer B Match TBCON.1 Timer B Overflow TBCON.2 TCCON.0 SYM.3 (EI, DI) Timer C Interrupt TCCON.1 Timer D Match TDCON.1 TINTPND.6 TDCON.0 Timer 1 Match/Capture TINTPND.4 T1CON.1 Timer 1 Overflow T1CON.0 P1INT.0 P1INT.3 P1INT.1 P1INT.5 SIOCON.0 SIOCON.1 PWM Interrupt PWMCON.0 PWMCON.1 UART Transmit UARTPND.0 UARTCON.0 UARTPND.1 UARTCON.1 UART Receive P1.1 External Interrupt (INT1) SIO Interrupt P1.0 External Interrupt (INT0) Timer D Overflow
TINTPND.2 TINTPND.3 0000H 0001H
TINTPND.7
TINTPND.5
Figure 5-3. S3F9498 Interrupt Structure
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SAM88RCRI INSTRUCTION SET
6
OVERVIEW
SAM88RCRI INSTRUCTION SET
The SAM88RCRI instruction set is designed to support the large register file. It includes a full complement of 8-bit arithmetic and logic operations. There are 41 instructions. No special I/O instructions are necessary because I/O control and data registers are mapped directly into the register file. Flexible instructions for bit addressing, rotate, and shift operations complete the powerful data manipulation capabilities of the SAM88RCRI instruction set. REGISTER ADDRESSING To access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is specified. Paired registers can be used to construct 13-bit program memory or data memory addresses. For detailed information about register addressing, please refer to Chapter 2, "Address Spaces". ADDRESSING MODES There are six addressing modes: Register (R), Indirect Register (IR), Indexed (X), Direct (DA), Relative (RA), and Immediate (IM). For detailed descriptions of these addressing modes, please refer to Chapter 3, "Addressing Modes".
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Table 6-1. Instruction Group Summary Mnemonic Operands Instruction
Load Instructions CLR LD LDC LDE LDCD LDED LDCI LDEI POP PUSH dst dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst src Clear Load Load program memory Load external data memory Load program memory and decrement Load external data memory and decrement Load program memory and increment Load external data memory and increment Pop from stack Push to stack
Arithmetic Instructions ADC ADD CP DEC INC SBC SUB dst,src dst,src dst,src dst dst dst,src dst,src Add with carry Add Compare Decrement Increment Subtract with carry Subtract
Logic Instructions AND COM OR XOR dst,src dst dst,src dst,src Logical AND Complement Logical OR Logical exclusive OR
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SAM88RCRI INSTRUCTION SET
Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction
Program Control Instructions CALL IRET JP JP JR RET cc,dst dst cc,dst dst Call procedure Interrupt return Jump on condition code Jump unconditional Jump relative on condition code Return
Bit Manipulation Instructions TCM TM dst,src dst,src Test complement under mask Test under mask
Rotate and Shift Instructions RL RLC RR RRC SRA dst dst dst dst dst Rotate left Rotate left through carry Rotate right Rotate right through carry Shift right arithmetic
CPU Control Instructions CCF DI EI IDLE NOP RCF SCF STOP Complement carry flag Disable interrupts Enable interrupts Enter Idle mode No operation Reset carry flag Set carry flag Enter stop mode
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FLAGS REGISTER (FLAGS) The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these bits, FLAGS.4-FLAGS.7, can be tested and used with conditional jump instructions; FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load instruction. Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags register. For example, the AND instruction updates the Zero, Sign and Overflow flags based on the outcome of the AND instruction. If the AND instruction uses the Flags register as the destination, then simultaneously, two write will occur to the Flags register producing an unpredictable result.
System Flags Register (FLAGS) D5H, R/W MSB Carry flag (C) Not mapped Zero flag (Z) .7 .6 .5 .4 .3 .2 .1 .0 LSB
Sign flag (S)
Overflow flag (V)
Figure 6-1. System Flags Register (FLAGS) FLAG DESCRIPTIONS Overflow Flag (FLAGS.4, V) The V flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than - 128. It is also cleared to "0" following logic operations. Sign Flag (FLAGS.5, S) Following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the MSB of the result. A logic zero indicates a positive number and a logic one indicates a negative number. Zero Flag (FLAGS.6, Z) For arithmetic and logic operations, the Z flag is set to "1" if the result of the operation is zero. For operations that test register bits, and for shift and rotate operations, the Z flag is set to "1" if the result is logic zero. Carry Flag (FLAGS.7, C) The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the specified register. Program instructions can set, clear, or complement the carry flag.
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SAM88RCRI INSTRUCTION SET
INSTRUCTION SET NOTATION Table 6-2. Flag Notation Conventions Flag C Z S V 0 1 * - x Carry flag Zero flag Sign flag Overflow flag Cleared to logic zero Set to logic one Set or cleared according to operation Value is unaffected Value is undefined Description
Table 6-3. Instruction Set Symbols Symbol dst src @ PC FLAGS # H D B opc Source operand Indirect register address prefix Program counter Flags register (D5H) Immediate operand or register address prefix Hexadecimal number suffix Decimal number suffix Binary number suffix Opcode Description Destination operand
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Table 6-4. Instruction Notation Conventions Notation cc r rr R RR Ir IR Irr IRR X XS xl da ra im Condition code Working register only Working register pair Register or working register Register pair or working register pair Indirect working register only Indirect working register pair only Indirect register pair or indirect working register pair Indexed addressing mode Indexed (short offset) addressing mode Indexed (long offset) addressing mode Direct addressing mode Relative addressing mode Immediate addressing mode Description Rn (n = 0-15) RRp (p = 0, 2, 4, ..., 14) reg or Rn (reg = 0-255, n = 0-15) reg or RRp (reg = 0-254, even number only, where p = 0, 2, ..., 14) @Rn (n = 0-15) @RRp (p = 0, 2, ..., 14) @RRp or @reg (reg = 0-254, even only, where p = 0, 2, ..., 14) #reg[Rn] (reg = 0-255, n = 0-15) #addr[RRp] (addr = range - 128 to + 127, where p = 0, 2, ..., 14) #addr [RRp] (addr = range 0-8191, where p = 0, 2, ..., 14) addr (addr = range 0-8191) addr (addr = number in the range + 127 to - 128 that is an offset relative to the address of the next instruction) #data (data = 0-255) Actual Operand Range See list of condition codes in Table 6-6.
Indirect register or indirect working register @Rn or @reg (reg = 0-255, n = 0-15)
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Table 6-5. Opcode Quick Reference OPCODE MAP LOWER NIBBLE (HEX) - U P P E R 0 1 2 3 4 5 N I B B L E 6 7 8 9 A B C H E X D E F CLR R1 RRC R1 SRA R1 RR R1 CLR IR1 RRC IR1 SRA IR1 RR IR1 LDCD r1,Irr2 RL R1 RL IR1 CP r1,r2 XOR r1,r2 CP r1,Ir2 XOR r1,Ir2 LDC r1,Irr2 LDC r2,Irr1 LDCI r1,Irr2 LD R2,R1 CALL IRR1 LD R2,IR1 LD IR2,R1 LD IR1,IM LD R1,IM CALL DA1 CP R2,R1 XOR R2,R1 CP IR2,R1 XOR IR2,R1 CP R1,IM XOR R1,IM POP R1 COM R1 PUSH R2 POP IR1 COM IR1 PUSH IR2 0 DEC R1 RLC R1 INC R1 JP IRR1 1 DEC IR1 RLC IR1 INC IR1 2 ADD r1,r2 ADC r1,r2 SUB r1,r2 SBC r1,r2 OR r1,r2 AND r1,r2 TCM r1,r2 TM r1,r2 3 ADD r1,Ir2 ADC r1,Ir2 SUB r1,Ir2 SBC r1,Ir2 OR r1,Ir2 AND r1,Ir2 TCM r1,Ir2 TM r1,Ir2 4 ADD R2,R1 ADC R2,R1 SUB R2,R1 SBC R2,R1 OR R2,R1 AND R2,R1 TCM R2,R1 TM R2,R1 5 ADD IR2,R1 ADC IR2,R1 SUB IR2,R1 SBC IR2,R1 OR IR2,R1 AND IR2,R1 TCM IR2,R1 TM IR2,R1 6 ADD R1,IM ADC R1,IM SUB R1,IM SBC R1,IM OR R1,IM AND R1,IM TCM R1,IM TM R1,IM LD r1, x, r2 LD r2, x, r1 LDC r1, Irr2, xL LDC r2, Irr2, xL LD r1, Ir2 LD Ir1, r2 LDC r1, Irr2, xs LDC r2, Irr1, xs 7
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Table 6-5. Opcode Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX) - U P 0 1 8 LD r1,R2 9 LD r2,R1 A B JR cc,RA C LD r1,IM D JP cc,DA E INC r1 F
P E R
2 3 4 5
N I B B L E
6 7 8 9 A B C
IDLE STOP DI EI RET IRET RCF SCF CCF LD r1,R2 LD r2,R1 JR cc,RA LD r1,IM JP cc,DA INC r1 NOP
H E X
D E F
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SAM88RCRI INSTRUCTION SET
CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6. The carry (C), zero (Z), sign (S), and overflow (V) flags are used to control the operation of conditional jump instructions. Table 6-6. Condition Codes Binary 0000 1000 0111 (1) 1111 (1) 0110 (1) 1110 (1) 1101 0101 0100 1100 0110 (1) 1110 (1) 1001 0001 1010 0010 1111 (1) 0111 (1) 1011 0011 Mnemonic F T C NC Z NZ PL MI OV NOV EQ NE GE LT GT LE UGE ULT UGT ULE Always true Carry No carry Zero Not zero Plus Minus Overflow No overflow Equal Not equal Greater than or equal Less than Greater than Less than or equal Unsigned greater than or equal Unsigned less than Unsigned greater than Unsigned less than or equal C=1 C=0 Z=1 Z=0 S=0 S=1 V=1 V=0 Z=1 Z=0 (S XOR V) = 0 (S XOR V) = 1 (Z OR (S XOR V)) = 0 (Z OR (S XOR V)) = 1 C=0 C=1 (C = 0 AND Z = 0) = 1 (C OR Z) = 1 Description Always false Flags Set - -
NOTES: 1. It indicates condition codes that are related to two different mnemonics but which test the same flag. For example, Z and EQ are both true if the zero flag (Z) is set, but after an ADD instruction, Z would probably be used; after a CP instruction, however, EQ would probably be used. 2. For operations involving unsigned numbers, the special condition codes UGE, ULT, UGT, and ULE must be used.
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INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM88RCRI instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The following information is included in each instruction description: -- Instruction name (mnemonic) -- Full instruction name -- Source/destination format of the instruction operand -- Shorthand notation of the instruction's operation -- Textual description of the instruction's effect -- Specific flag settings affected by the instruction -- Detailed description of the instruction's format, execution time, and addressing mode(s) -- Programming example(s) explaining how to use the instruction
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SAM88RCRI INSTRUCTION SET
ADC -- Add with Carry
ADC Operation: dst,src dst _ dst + src + c The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed. In multiple precision arithmetic, this instruction permits the carry from the addition of low-order operands to be carried into the addition of high-order operands. Flags: C: Z: S: V: Set if there is a carry from the most significant bit of the result; cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise.
Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) 12 13 14 15 16 Addr Mode dst src r r R R R r lr R IR IM
Examples:
Given: R1 = 10H, R2 = 03H, C flag = "1", register 01H = 20H, register 02H = 03H, and register 03H = 0AH: ADC ADC ADC ADC ADC R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#11H (R) (R) (R) (R) (R) R1 = 14H, R2 = 03H R1 = 1BH, R2 = 03H Register 01H = 24H, register 02H = 03H Register 01H = 2BH, register 02H = 03H Register 01H = 32H
In the first example, destination register R1 contains the value 10H, the carry flag is set to "1", and the source working register R2 contains the value 03H. The statement "ADC R1,R2" adds 03H and the carry flag value ("1") to the destination value 10H, leaving 14H in register R1.
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ADD -- Add
ADD Operation: dst,src dst _ dst + src The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed. Flags: C: Z: S: V: Set if there is a carry from the most significant bit of the result; cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise.
Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) 02 03 04 05 06 Addr Mode dst src r r R R R r lr R IR IM
Examples:
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH: ADD ADD ADD ADD ADD R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#25H (R) (R) (R) (R) (R) R1 = 15H, R2 = 03H R1 = 1CH, R2 = 03H Register 01H = 24H, register 02H = 03H Register 01H = 2BH, register 02H = 03H Register 01H = 46H
In the first example, destination working register R1 contains 12H and the source working register R2 contains 03H. The statement "ADD R1,R2" adds 03H to 12H, leaving the value 15H in register R1.
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SAM88RCRI INSTRUCTION SET
AND -- Logical AND
AND Operation: dst,src dst _ dst AND src The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the source are unaffected. Flags: C: Z: S: V: Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) 52 53 54 55 56 Addr Mode dst src r r R R R r lr R IR IM Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always cleared to "0".
Examples:
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH: AND AND AND AND AND R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#25H (R) (R) (R) (R) (R) R1 = 02H, R2 = 03H R1 = 02H, R2 = 03H Register 01H = 01H, register 02H = 03H Register 01H = 00H, register 02H = 03H Register 01H = 21H
In the first example, destination working register R1 contains the value 12H and the source working register R2 contains 03H. The statement "AND R1,R2" logically ANDs the source operand 03H with the destination operand value 12H, leaving the value 02H in register R1.
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CALL -- Call Procedure
CALL Operation: dst SP @SP SP @SP PC SP - 1 PCL SP -1 PCH dst
The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified destination address is then loaded into the program counter and points to the first instruction of a procedure. At the end of the procedure the return instruction (RET) can be used to return to the original program flow. RET pops the top of the stack back into the program counter. Flags: Format: Bytes opc opc dst dst 3 2 Cycles 14 12 Opcode (Hex) F6 F4 Addr Mode dst DA IRR No flags are affected.
Examples:
Given: R0 = 15H, R1 = 21H, PC = 1A47H, and SP = 0B2H: CALL 1521H (R) SP = 0B0H (Memory locations 00H = 1AH, 01H = 4AH, where 4AH is the address that follows the instruction.) SP = 0B0H (00H = 1AH, 01H = 49H)
CALL
@RR0
(R)
In the first example, if the program counter value is 1A47H and the stack pointer contains the value 0B2H, the statement "CALL 1521H" pushes the current PC value onto the top of the stack. The stack pointer now points to memory location 00H. The PC is then loaded with the value 1521H, the address of the first instruction in the program sequence to be executed. If the contents of the program counter and stack pointer are the same as in the first example, the statement "CALL @RR0" produces the same result except that the 49H is stored in stack location 01H (because the two-byte instruction format was used). The PC is then loaded with the value 1521H, the address of the first instruction in the program sequence to be executed.
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SAM88RCRI INSTRUCTION SET
CCF -- Complement Carry Flag
CCF Operation: C _ NOT C The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one. Flags: C: Complemented. No other flags are affected.
Format: Bytes opc 1 Cycles 4 Opcode (Hex) EF
Example:
Given: The carry flag = "0": CCF If the carry flag = "0", the CCF instruction complements it in the FLAGS register (0D5H), changing its value from logic zero to logic one.
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CLR -- Clear
CLR Operation: dst dst _ "0" The destination location is cleared to "0". Flags: Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) B0 B1 Addr Mode dst R IR No flags are affected.
Examples:
Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH: CLR CLR 00H @01H (R) (R) Register 00H = 00H Register 01H = 02H, register 02H = 00H
In Register (R) addressing mode, the statement "CLR 00H" clears the destination register 00H value to 00H. In the second example, the statement "CLR @01H" uses Indirect Register (IR) addressing mode to clear the 02H register value to 00H.
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SAM88RCRI INSTRUCTION SET
COM -- Complement
COM Operation: dst dst _ NOT dst The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. Flags: C: Z: S: V: Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) 60 61 Addr Mode dst R IR Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always reset to "0".
Examples:
Given: R1 = 07H and register 07H = 0F1H: COM COM R1 @R1 (R) (R) R1 = 0F8H R1 = 07H, register 07H = 0EH
In the first example, destination working register R1 contains the value 07H (00000111B). The statement "COM R1" complements all the bits in R1: all logic ones are changed to logic zeros, and vice-versa, leaving the value 0F8H (11111000B). In the second example, Indirect Register (IR) addressing mode is used to complement the value of destination register 07H (11110001B), leaving the new value 0EH (00001110B).
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CP -- Compare
CP Operation: dst,src dst - src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison. Flags: C: Z: S: V: Set if a "borrow" occurred (src > dst); cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand; cleared otherwise.
Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) A2 A3 A4 A5 A6 Addr Mode dst src r r R R R r lr R IR IM
Examples:
1. Given: R1 = 02H and R2 = 03H: CP R1,R2 Set the C and S flags
Destination working register R1 contains the value 02H and source register R2 contains the value 03H. The statement "CP R1,R2" subtracts the R2 value (source/subtrahend) from the R1 value (destination/minuend). Because a "borrow" occurs and the difference is negative, C and S are "1". 2. Given: R1 = 05H and R2 = 0AH: CP JP INC LD R1,R2 UGE,SKIP R1 R3,R1
SKIP
In this example, destination working register R1 contains the value 05H which is less than the contents of the source working register R2 (0AH). The statement "CP R1,R2" generates C = "1" and the JP instruction does not jump to the SKIP location. After the statement "LD R3,R1" executes, the value 06H remains in working register R3.
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SAM88RCRI INSTRUCTION SET
DEC -- Decrement
DEC Operation: dst dst _ dst - 1 The contents of the destination operand are decremented by one. Flags: C: Z: S: V: Unaffected. Set if the result is "0"; cleared otherwise. Set if result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, dst value is - 128 (80H) and result value is + 127 (7FH); cleared otherwise.
Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) 00 01 Addr Mode dst R IR
Examples:
Given: R1 = 03H and register 03H = 10H: DEC DEC R1 @R1 (R) (R) R1 = 02H Register 03H = 0FH
In the first example, if working register R1 contains the value 03H, the statement "DEC R1" decrements the hexadecimal value by one, leaving the value 02H. In the second example, the statement "DEC @R1" decrements the value 10H contained in the destination register 03H by one, leaving the value 0FH.
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DI -- Disable Interrupts
DI Operation: SYM (3) _ 0 Bit zero of the system mode register, SYM.3, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled. Flags: Format: Bytes opc 1 Cycles 4 Opcode (Hex) 8F No flags are affected.
Example:
Given: SYM = 08H: DI If the value of the SYM register is 08H, the statement "DI" leaves the new value 00H in the register and clears SYM.3 to "0", disabling interrupt processing.
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SAM88RCRI INSTRUCTION SET
EI -- Enable Interrupts
EI Operation: SYM (3) _ 1 An EI instruction sets bit 3 of the system mode register, SYM.3 to "1". This allows interrupts to be serviced as they occur. If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when you execute the EI instruction. Flags: Format: Bytes opc 1 Cycles 4 Opcode (Hex) 9F No flags are affected.
Example:
Given: SYM = 00H: EI If the SYM register contains the value 00H, that is, if interrupts are currently disabled, the statement "EI" sets the SYM register to 08H, enabling all interrupts. (SYM.3 is the enable bit for global interrupt processing.)
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SAM88RCRI INSTRUCTION SET
S3C9498/F9498
IDLE -- Idle Operation
IDLE Operation: The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation. Flags: Format: Bytes opc 1 Cycles 4 Opcode (Hex) 6F Addr Mode src dst - - No flags are affected.
Example:
The instruction IDLE NOP NOP NOP stops the CPU clock but not the system clock.
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S3C9498/F9498
SAM88RCRI INSTRUCTION SET
INC -- Increment
INC Operation: dst dst _ dst + 1 The contents of the destination operand are incremented by one. Flags: C: Z: S: V: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is dst value is + 127 (7FH) and result is - 128 (80H); cleared otherwise.
Format: Bytes dst | opc 1 Cycles 4 Opcode (Hex) rE r = 0 to F opc dst 2 4 4 20 21 R IR Addr Mode dst r
Examples:
Given: R0 = 1BH, register 00H = 0CH, and register 1BH = 0FH: INC INC INC R0 00H @R0 (R) (R) (R) R0 = 1CH Register 00H = 0DH R0 = 1BH, register 01H = 10H
In the first example, if destination working register R0 contains the value 1BH, the statement "INC R0" leaves the value 1CH in that same register. The next example shows the effect an INC instruction has on register 00H, assuming that it contains the value 0CH. In the third example, INC is used in Indirect Register (IR) addressing mode to increment the value of register 1BH from 0FH to 10H.
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SAM88RCRI INSTRUCTION SET
S3C9498/F9498
IRET -- Interrupt Return
IRET Operation: IRET FLAGS _ @SP SP _ SP + 1 PC _ @SP SP _ SP + 2 SYM(2) _ 1 This instruction is used at the end of an interrupt service routine. It restores the flag register and the program counter. It also re-enables global interrupts. Flags: Format: IRET (Normal) opc Bytes 1 Cycles 10 12 Opcode (Hex) BF All flags are restored to their original settings (that is, the settings before the interrupt occurred).
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SAM88RCRI INSTRUCTION SET
JP -- Jump
JP JP Operation: cc,dst dst (Conditional) (Unconditional)
If cc is true, PC _ dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction is executed. The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair. Control then passes to the statement addressed by the PC.
Flags: Format: (1)
No flags are affected.
Bytes
(2)
Cycles 8
Opcode (Hex) ccD cc = 0 to F
Addr Mode dst DA
cc | opc
dst
3
opc
dst
2
8
30
IRR
NOTES: 1. The 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump. 2. In the first byte of the three-byte instruction format (conditional jump), the condition code and the op code are both four bits.
Examples:
Given: The carry flag (C) = "1", register 00 = 01H, and register 01 = 20H: JP JP C,LABEL_W @00H (R) (R) LABEL_W = 1000H, PC = 1000H PC = 0120H
The first example shows a conditional JP. Assuming that the carry flag is set to "1", the statement "JP C,LABEL_W" replaces the contents of the PC with the value 1000H and transfers control to that location. Had the carry flag not been set, control would then have passed to the statement immediately following the JP instruction. The second example shows an unconditional JP. The statement "JP @00" replaces the contents of the PC with the contents of the register pair 00H and 01H, leaving the value 0120H.
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SAM88RCRI INSTRUCTION SET
S3C9498/F9498
JR -- Jump Relative
JR Operation: cc,dst If cc is true, PC _ PC + dst If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise, the instruction following the JR instruction is executed (See list of condition codes). The range of the relative address is + 127, - 128, and the original value of the program counter is taken to be the address of the first instruction byte following the JR statement. Flags: Format: Bytes
(note)
No flags are affected.
Cycles 6
Opcode (Hex) ccB cc = 0 to F
Addr Mode dst RA
cc | opc
dst
2
NOTE: In the first byte of the two-byte instruction format, the condition code and the op code are each four bits.
Example:
Given: The carry flag = "1" and LABEL_X = 1FF7H: JR C,LABEL_X (R) PC = 1FF7H
If the carry flag is set (that is, if the condition code is true), the statement "JR C,LABEL_X" will pass control to the statement whose address is now in the PC. Otherwise, the program instruction following the JR would be executed.
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S3C9498/F9498
SAM88RCRI INSTRUCTION SET
LD -- Load
LD Operation: dst,src dst _ src The contents of the source are loaded into the destination. The source's contents are unaffected. Flags: Format: Bytes dst | opc src 2 Cycles 4 4 Opcode (Hex) rC r8 Addr Mode dst src r r IM R No flags are affected.
src | opc
dst
2
4
r9 r = 0 to F
R
r
opc
dst | src
2
4 4
C7 D7
r Ir
lr r
opc
src
dst
3
6 6
E4 E5
R R
R IR
opc
dst
src
3
6 6
E6 D6
R IR
IM IM
opc
src
dst
3
6
F5
IR
R
opc
dst | src
x
3
6
87
r
x [r]
opc
src | dst
x
3
6
97
x [r]
r
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SAM88RCRI INSTRUCTION SET
S3C9498/F9498
LD -- Load
LD Examples: (Continued) Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH: LD LD LD LD LD LD LD LD LD LD LD LD R0,#10H R0,01H 01H,R0 R1,@R0 @R0,R1 00H,01H 02H,@00H 00H,#0AH @00H,#10H @00H,02H R0,#LOOP[R1] #LOOP[R0],R1 (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) R0 = 10H R0 = 20H, register 01H = 20H Register 01H = 01H, R0 = 01H R1 = 20H, R0 = 01H R0 = 01H, R1 = 0AH, register 01H = 0AH Register 00H = 20H, register 01H = 20H Register 02H = 20H, register 00H = 01H Register 00H = 0AH Register 00H = 01H, register 01H = 10H Register 00H = 01H, register 01H = 02, register 02H = 02H R0 = 0FFH, R1 = 0AH Register 31H = 0AH, R0 = 01H, R1 = 0AH
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SAM88RCRI INSTRUCTION SET
LDC/LDE -- Load Memory
LDC/LDE Operation: dst,src dst _ src This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes "Irr" or "rr" values an even number for program memory and odd an odd number for data memory. Flags: Format: Bytes 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. opc opc opc opc opc opc opc opc opc opc
dst | src 2
No flags are affected.
Cycles
10
Opcode (Hex)
C3
Addr Mode dst src
r Irr
src | dst
2
10
D3
Irr
r
dst | src
XS XS XLL XLL DAL DAL DAL DAL XLH XLH DAH DAH DAH DAH
3
12
E7
r
XS [rr]
src | dst
3
12
F7
XS [rr]
r
dst | src
4
14
A7
r
XL [rr]
src | dst
4
14
B7
XL [rr]
r
dst | 0000
4
14
A7
r
DA
src | 0000
4
14
B7
DA
r
dst | 0001
4
14
A7
r
DA
src | 0001
4
14
B7
DA
r
NOTES: 1. The source (src) or working register pair [rr] for formats 5 and 6 cannot use register pair 0-1. 2. For formats 3 and 4, the destination address "XS [rr]" and the source address "XS [rr]" are each one byte. 3. For formats 5 and 6, the destination address "XL [rr]" and the source address "XL [rr]" are each two bytes. 4. The DA and r source values for formats 7 and 8 are used to address program memory; the second set of values, used in formats 9 and 10, are used to address data memory.
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SAM88RCRI INSTRUCTION SET
S3C9498/F9498
LDC/LDE -- Load Memory
LDC/LDE Examples: (Continued) Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H, R4 = 00H, R5 = 60H; Program memory locations 0061 = AAH, 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory locations 0061H = BBH, 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H: LDC LDE R0,@RR2 R0,@RR2 ; R0 _ contents of program memory location 0104H ; R0 = 1AH, R2 = 01H, R3 = 04H ; R0 _ contents of external data memory location 0104H ; R0 = 2AH, R2 = 01H, R3 = 04H ; 11H (contents of R0) is loaded into program memory ; location 0104H (RR2), ; working registers R0, R2, R3 _ no change ; 11H (contents of R0) is loaded into external data memory ; location 0104H (RR2), ; working registers R0, R2, R3 _ no change ; R0 _ contents of program memory location 0061H ; (01H + RR4), ; R0 = AAH, R2 = 00H, R3 = 60H ; R0 _ contents of external data memory location 0061H ; (01H + RR4), R0 = BBH, R4 = 00H, R5 = 60H ; 11H (contents of R0) is loaded into program memory location ; 0061H (01H + 0060H) ; 11H (contents of R0) is loaded into external data memory ; location 0061H (01H + 0060H)
LDC (note) @RR2,R0
LDE
@RR2,R0
LDC
R0,#01H[RR4]
LDE
R0,#01H[RR4]
LDC (note) #01H[RR4],R0 LDE LDC LDE LDC LDE #01H[RR4],R0
R0,#1000H[RR2] ; R0 _ contents of program memory location 1104H ; (1000H + 0104H), R0 = 88H, R2 = 01H, R3 = 04H R0,#1000H[RR2] ; R0 _ contents of external data memory location 1104H ; (1000H + 0104H), R0 = 98H, R2 = 01H, R3 = 04H R0,1104H R0,1104H ; R0 _ contents of program memory location 1104H, R0 = 88H ; R0 _ contents of external data memory location 1104H, ; R0 = 98H ; 11H (contents of R0) is loaded into program memory location ; 1105H, (1105H) _ 11H ; 11H (contents of R0) is loaded into external data memory ; location 1105H, (1105H) _ 11H
LDC (note) 1105H,R0 LDE 1105H,R0
NOTE: These instructions are not supported by masked ROM type devices.
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SAM88RCRI INSTRUCTION SET
LDCD/LDED -- Load Memory and Decrement
LDCD/LDED Operation: dst,src dst _ src rr _ rr - 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then decremented. The contents of the source are unaffected. LDCD references program memory and LDED references external data memory. The assembler makes "Irr" an even number for program memory and an odd number for data memory. Flags: Format: Bytes opc dst | src 2 Cycles 10 Opcode (Hex) E2 Addr Mode dst src r Irr No flags are affected.
Examples:
Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory location 1033H = 0CDH, and external data memory location 1033H = 0DDH: LDCD R8,@RR6 ; 0CDH (contents of program memory location 1033H) is loaded ; into R8 and RR6 is decremented by one ; R8 = 0CDH, R6 = 10H, R7 = 32H (RR6 _ RR6 - 1) ; 0DDH (contents of data memory location 1033H) is loaded ; into R8 and RR6 is decremented by one (RR6 _ RR6 - 1) ; R8 = 0DDH, R6 = 10H, R7 = 32H
LDED
R8,@RR6
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SAM88RCRI INSTRUCTION SET
S3C9498/F9498
LDCI/LDEI -- LOAD MEMORY AND INCREMENT
LDCI/LDEI Operation: dst,src dst _ src rr _ rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then incremented automatically. The contents of the source are unaffected. LDCI refers to program memory and LDEI refers to external data memory. The assembler makes "Irr" even for program memory and odd for data memory. Flags: Format: Bytes opc dst | src 2 Cycles 10 Opcode (Hex) E3 Addr Mode dst src r Irr No flags are affected.
Examples:
Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory locations 1033H = 0CDH and 1034H = 0C5H; external data memory locations 1033H = 0DDH and 1034H = 0D5H: LDCI R8,@RR6 ; 0CDH (contents of program memory location 1033H) is loaded ; into R8 and RR6 is incremented by one (RR6 _ RR6 + 1) ; R8 = 0CDH, R6 = 10H, R7 = 34H ; 0DDH (contents of data memory location 1033H) is loaded ; into R8 and RR6 is incremented by one (RR6 _ RR6 + 1) ; R8 = 0DDH, R6 = 10H, R7 = 34H
LDEI
R8,@RR6
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SAM88RCRI INSTRUCTION SET
NOP -- No Operation
NOP Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration. No flags are affected.
Flags: Format:
Bytes opc 1
Cycles 4
Opcode (Hex) FF
Example:
When the instruction NOP is encountered in a program, no operation occurs. Instead, there is a delay in instruction execution time.
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SAM88RCRI INSTRUCTION SET
S3C9498/F9498
OR -- Logical OR
OR Operation: dst,src dst _ dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is stored. Flags: C: Z: S: V: Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) 42 43 44 45 46 Addr Mode dst src r r R R R r lr R IR IM Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always cleared to "0".
Examples:
Given: R0 = 15H, R1 = 2AH, R2 = 01H, register 00H = 08H, register 01H = 37H, and register 08H = 8AH: OR OR OR OR OR R0,R1 R0,@R2 00H,01H 01H,@00H 00H,#02H (R) (R) (R) (R) (R) R0 = 3FH, R1 = 2AH R0 = 37H, R2 = 01H, register 01H = 37H Register 00H = 3FH, register 01H = 37H Register 00H = 08H, register 01H = 0BFH Register 00H = 0AH
In the first example, if working register R0 contains the value 15H and register R1 the value 2AH, the statement "OR R0,R1" logical-ORs the R0 and R1 register contents and stores the result (3FH) in destination register R0. The other examples show the use of the logical OR instruction with the various addressing modes and formats.
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SAM88RCRI INSTRUCTION SET
POP -- Pop From Stack
POP Operation: dst dst _ @SP SP _ SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one. Flags: Format: Bytes opc dst 2 Cycles 8 8 Opcode (Hex) 50 51 Addr Mode dst R IR No flags affected.
Examples:
Given: Register 00H = 01H, register 01H = 1BH, SP (0D9H) = 0BBH, and stack register 0BBH = 55H: POP POP 00H @00H (R) (R) Register 00H = 55H, SP = 0BCH Register 00H = 01H, register 01H = 55H, SP = 0BCH
In the first example, general register 00H contains the value 01H. The statement "POP 00H" loads the contents of location 0BBH (55H) into destination register 00H and then increments the stack pointer by one. Register 00H then contains the value 55H and the SP points to location 0BCH.
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SAM88RCRI INSTRUCTION SET
S3C9498/F9498
PUSH -- Push To Stack
PUSH Operation: src SP _ SP - 1 @SP _ src A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack. Flags: Format: Bytes opc src 2 Cycles 8 8 Opcode (Hex) 70 71 Addr Mode dst R IR No flags are affected.
Examples:
Given: Register 40H = 4FH, register 4FH = 0AAH, SP = 0C0H: PUSH PUSH 40H @40H (R) Register 40H = 4FH, stack register 0BFH = 4FH, SP = 0BFH Register 40H = 4FH, register 4FH = 0AAH, stack register 0BFH = 0AAH, SP = 0BFH
(R)
In the first example, if the stack pointer contains the value 0C0H, and general register 40H the value 4FH, the statement "PUSH 40H" decrements the stack pointer from 0C0 to 0BFH. It then loads the contents of register 40H into location 0BFH. Register 0BFH then contains the value 4FH and SP points to location 0BFH.
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SAM88RCRI INSTRUCTION SET
RCF -- Reset Carry Flag
RCF Operation: RCF C_0 The carry flag is cleared to logic zero, regardless of its previous value. Flags: C: Cleared to "0". No other flags are affected. Format: Bytes opc 1 Cycles 4 Opcode (Hex) CF
Example:
Given: C = "1" or "0": The instruction RCF clears the carry flag (C) to logic zero.
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SAM88RCRI INSTRUCTION SET
S3C9498/F9498
RET -- Return
RET Operation: PC _ @SP SP _ SP + 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter. The next statement that is executed is the one that is addressed by the new program counter value. Flags: Format: Bytes opc 1 Cycles 8 10 Opcode (Hex) AF No flags are affected.
Example:
Given: SP = 0BCH, (SP) = 101AH, and PC = 1234: RET (R) PC = 101AH, SP = 0BEH
The statement "RET" pops the contents of stack pointer location 0BCH (10H) into the high byte of the program counter. The stack pointer then pops the value in location 0BDH (1AH) into the PC's low byte and the instruction at location 101AH is executed. The stack pointer now points to memory location 0BEH.
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SAM88RCRI INSTRUCTION SET
RL -- Rotate Left
RL Operation: dst C _ dst (7) dst (0) _ dst (7) dst (n + 1) _ dst (n), n = 0-6 The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag.
7 C 0
Flags:
C: Z: S: V:
Set if the bit rotated from the most significant bit position (bit 7) was "1". Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise.
Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) 90 91 Addr Mode dst R IR
Examples:
Given: Register 00H = 0AAH, register 01H = 02H and register 02H = 17H: RL RL 00H @01H (R) (R) Register 00H = 55H, C = "1" Register 01H = 02H, register 02H = 2EH, C = "0"
In the first example, if general register 00H contains the value 0AAH (10101010B), the statement "RL 00H" rotates the 0AAH value left one bit position, leaving the new value 55H (01010101B) and setting the carry and overflow flags.
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SAM88RCRI INSTRUCTION SET
S3C9498/F9498
RLC -- Rotate Left Through Carry
RLC Operation: dst dst (0) _ C C _ dst (7) dst (n + 1) _ dst (n), n = 0-6 The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C); the initial value of the carry flag replaces bit zero.
7 C 0
Flags:
C: Z: S: V:
Set if the bit rotated from the most significant bit position (bit 7) was "1". Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise.
Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) 10 11 Addr Mode dst R IR
Examples:
Given: Register 00H = 0AAH, register 01H = 02H, and register 02H = 17H, C = "0": RLC RLC 00H @01H (R) (R) Register 00H = 54H, C = "1" Register 01H = 02H, register 02H = 2EH, C = "0"
In the first example, if general register 00H has the value 0AAH (10101010B), the statement "RLC 00H" rotates 0AAH one bit position to the left. The initial value of bit 7 sets the carry flag and the initial value of the C flag replaces bit zero of register 00H, leaving the value 55H (01010101B). The MSB of register 00H resets the carry flag to "1" and sets the overflow flag.
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SAM88RCRI INSTRUCTION SET
RR -- Rotate Right
RR Operation: dst C _ dst (0) dst (7) _ dst (0) dst (n) _ dst (n + 1), n = 0-6 The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).
7 C 0
Flags:
C: Z: S: V:
Set if the bit rotated from the least significant bit position (bit zero) was "1". Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise.
Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) E0 E1 Addr Mode dst R IR
Examples:
Given: Register 00H = 31H, register 01H = 02H, and register 02H = 17H: RR RR 00H @01H (R) (R) Register 00H = 98H, C = "1" Register 01H = 02H, register 02H = 8BH, C = "1"
In the first example, if general register 00H contains the value 31H (00110001B), the statement "RR 00H" rotates this value one bit position to the right. The initial value of bit zero is moved to bit 7, leaving the new value 98H (10011000B) in the destination register. The initial bit zero also resets the C flag to "1" and the sign flag and overflow flag are also set to "1".
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SAM88RCRI INSTRUCTION SET
S3C9498/F9498
RRC -- Rotate Right Through Carry
RRC Operation: dst dst (7) _ C C _ dst (0) dst (n) _ dst (n + 1), n = 0-6 The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit 7 (MSB).
7 C 0
Flags:
C: Z: S: V:
Set if the bit rotated from the least significant bit position (bit zero) was "1". Set if the result is "0" cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise.
Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) C0 C1 Addr Mode dst R IR
Examples:
Given: Register 00H = 55H, register 01H = 02H, register 02H = 17H, and C = "0": RRC RRC 00H @01H (R) (R) Register 00H = 2AH, C = "1" Register 01H = 02H, register 02H = 0BH, C = "1"
In the first example, if general register 00H contains the value 55H (01010101B), the statement "RRC 00H" rotates this value one bit position to the right. The initial value of bit zero ("1") replaces the carry flag and the initial value of the C flag ("1") replaces bit 7. This leaves the new value 2AH (00101010B) in destination register 00H. The sign flag and overflow flag are both cleared to "0".
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SAM88RCRI INSTRUCTION SET
SBC -- Subtract With Carry
SBC Operation: dst,src dst _ dst - src - c The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's-complement of the source operand to the destination operand. In multiple precision arithmetic, this instruction permits the carry ("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of high-order operands. Flags: C: Z: S: V: Set if a borrow occurred (src > dst); cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign of the result is the same as the sign of the source; cleared otherwise.
Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) 32 33 34 35 36 Addr Mode dst src r r R R R r lr R IR IM
Examples:
Given: R1 = 10H, R2 = 03H, C = "1", register 01H = 20H, register 02H = 03H, and register 03H = 0AH: SBC SBC SBC SBC SBC R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#8AH (R) (R) (R) (R) (R) R1 = 0CH, R2 = 03H R1 = 05H, R2 = 03H, register 03H = 0AH Register 01H = 1CH, register 02H = 03H Register 01H = 15H,register 02H = 03H, register 03H = 0AH Register 01H = 95H; C, S, and V = "1"
In the first example, if working register R1 contains the value 10H and register R2 the value 03H, the statement "SBC R1,R2" subtracts the source value (03H) and the C flag value ("1") from the destination (10H) and then stores the result (0CH) in register R1.
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SAM88RCRI INSTRUCTION SET
S3C9498/F9498
SCF -- Set Carry Flag
SCF Operation: C_1 The carry flag (C) is set to logic one, regardless of its previous value. Flags: C: Set to "1". No other flags are affected. Format: Bytes opc 1 Cycles 4 Opcode (Hex) DF
Example:
The statement SCF sets the carry flag to logic one.
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S3C9498/F9498
SAM88RCRI INSTRUCTION SET
SRA -- Shift Right Arithmetic
SRA Operation: dst dst (7) _ dst (7) C _ dst (0) dst (n) _ dst (n + 1), n = 0-6 An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into bit position 6.
76 C 0
Flags:
C: Z: S: V:
Set if the bit shifted from the LSB position (bit zero) was "1". Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Always cleared to "0".
Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) D0 D1 Addr Mode dst R IR
Examples:
Given: Register 00H = 9AH, register 02H = 03H, register 03H = 0BCH, and C = "1": SRA SRA 00H @02H (R) (R) Register 00H = 0CD, C = "0" Register 02H = 03H, register 03H = 0DEH, C = "0"
In the first example, if general register 00H contains the value 9AH (10011010B), the statement "SRA 00H" shifts the bit values in register 00H right one bit position. Bit zero ("0") clears the C flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). This leaves the value 0CDH (11001101B) in destination register 00H.
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SAM88RCRI INSTRUCTION SET
S3C9498/F9498
STOP -- Stop Operation
STOP Operation: The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode can be released by an external reset operation or External interrupt input. For the reset operation, the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed. No flags are affected.
Flags: Format:
Bytes opc 1
Cycles 4
Opcode (Hex) 7F
Addr Mode src dst - -
Example:
The statement LD STOP NOP NOP NOP halts all microcontroller operations. When STOPCON register is not #0A5H value, if you use STOP instruction, PC is changed to reset address. STOPCON, #0A5H
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S3C9498/F9498
SAM88RCRI INSTRUCTION SET
SUB -- Subtract
SUB Operation: dst,src dst _ dst - src The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source operand to the destination operand. Flags: C: Z: S: V: Set if a "borrow" occurred; cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand; cleared otherwise.
Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) 22 23 24 25 26 Addr Mode dst src r r R R R r lr R IR IM
Examples:
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH: SUB SUB SUB SUB SUB SUB R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#90H 01H,#65H (R) (R) (R) (R) (R) (R) R1 = 0FH, R2 = 03H R1 = 08H, R2 = 03H Register 01H = 1EH, register 02H = 03H Register 01H = 17H, register 02H = 03H Register 01H = 91H; C, S, and V = "1" Register 01H = 0BCH; C and S = "1", V = "0"
In the first example, if working register R1 contains the value 12H and if register R2 contains the value 03H, the statement "SUB R1,R2" subtracts the source value (03H) from the destination value (12H) and stores the result (0FH) in destination register R1.
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SAM88RCRI INSTRUCTION SET
S3C9498/F9498
TCM
TCM
-- Test Complement Under Mask
dst,src (NOT dst) AND src This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask). The TCM statement complements the destination operand, which is then ANDed with the source mask. The zero (Z) flag can then be checked to determine the result. The destination and source operands are unaffected.
Operation:
Flags:
C: Z: S: V:
Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always cleared to "0".
Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) 62 63 64 65 66 Addr Mode dst src r r R R R r lr R IR IM
Examples:
Given: R0 = 0C7H, R1 = 02H, R2 = 12H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H: TCM TCM TCM TCM TCM R0,R1 R0,@R1 00H,01H 00H,@01H 00H,#34 (R) (R) (R) (R) (R) R0 = 0C7H, R1 = 02H, Z = "1" R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0" Register 00H = 2BH, register 01H = 02H, Z = "1" Register 00H = 2BH, register 01H = 02H, register 02H = 23H, Z = "1" Register 00H = 2BH, Z = "0"
In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1 the value 02H (00000010B), the statement "TCM R0,R1" tests bit one in the destination register for a "1" value. Because the mask value corresponds to the test bit, the Z flag is set to logic one and can be tested to determine the result of the TCM operation.
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S3C9498/F9498
SAM88RCRI INSTRUCTION SET
TM -- Test Under Mask
TM Operation: dst,src dst AND src This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is ANDed with the destination operand. The zero (Z) flag can then be checked to determine the result. The destination and source operands are unaffected. Flags: C: Z: S: V: Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) 72 73 74 75 76 Addr Mode dst src r r R R R r lr R IR IM Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always reset to "0".
Examples:
Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H: TM TM TM TM TM R0,R1 R0,@R1 00H,01H 00H,@01H 00H,#54H (R) (R) (R) (R) (R) R0 = 0C7H, R1 = 02H, Z = "0" R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0" Register 00H = 2BH, register 01H = 02H, Z = "0" Register 00H = 2BH, register 01H = 02H, register 02H = 23H, Z = "0" Register 00H = 2BH, Z = "1"
In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1 the value 02H (00000010B), the statement "TM R0,R1" tests bit one in the destination register for a "0" value. Because the mask value does not match the test bit, the Z flag is cleared to logic zero and can be tested to determine the result of the TM operation.
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SAM88RCRI INSTRUCTION SET
S3C9498/F9498
XOR -- Logical Exclusive OR
XOR Operation: dst,src dst _ dst XOR src The source operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the operands are different; otherwise, a "0" bit is stored. Flags: C: Z: S: V: Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) B2 B3 B4 B5 B6 Addr Mode dst src r r R R R r lr R IR IM Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always reset to "0".
Examples:
Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H: XOR XOR XOR XOR XOR R0,R1 R0,@R1 00H,01H 00H,@01H 00H,#54H (R) (R) (R) (R) (R) R0 = 0C5H, R1 = 02H R0 = 0E4H, R1 = 02H, register 02H = 23H Register 00H = 29H, register 01H = 02H Register 00H = 08H, register 01H = 02H, register 02H = 23H Register 00H = 7FH
In the first example, if working register R0 contains the value 0C7H and if register R1 contains the value 02H, the statement "XOR R0,R1" logically exclusive-ORs the R1 value with the R0 value and stores the result (0C5H) in the destination register R0.
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S3C9498/F9498
CLOCK CIRCUIT
7
OVERVIEW
CLOCK CIRCUIT
The clock frequency generation for the S3C9498/F9498 by an external crystal can range from 1 MHz to 8 MHz. The maximum CPU clock frequency is 8 MHz. The XIN and XOUT pins connect the external oscillator or clock source to the on-chip clock circuit. SYSTEM CLOCK CIRCUIT The system clock circuit has the following components: -- External crystal or ceramic resonator oscillation source (or an external clock source) -- Oscillator stop and wake-up functions -- Programmable frequency divider for the CPU clock (fxx divided by 1, 2, 8, or 16) -- System clock control register, CLKCON -- STOP control register, STPCON
C1
XIN
S3F9498
C2
XOUT
Figure 7-1. Main Oscillator Circuit (Crystal or Ceramic Oscillator) CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect clock oscillation as follows: -- In Stop mode, the main oscillator "freezes", halting the CPU and peripherals. The contents of the register file and current system register values are retained. Stop mode is released, and the oscillator started, by a reset operation or by an external interrupt with RC-delay noise filter (for S3C9498/F9498, INT0-INT1). -- In Idle mode, the internal clock signal is gated off to the CPU, but not to interrupt control and the timer. The current CPU status is preserved, including stack pointer, program counter, and flags. Data in the register file is retained. Idle mode is released by a reset or by an interrupt (external or internally-generated).
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CLOCK CIRCUIT
S3C9498/F9498
SYSTEM CLOCK CONTROL REGISTER (CLKCON) The system clock control register, CLKCON, is located at address D0H. It is read/write addressable and has the following functions: -- Oscillator frequency divide-by value After the main oscillator is activated, and the fxx/16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the CPU clock speed to fxx/8, fxx/2, or fxx/1.
System Clock Control Register (CLKCON) D4H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used Oscillator IRQ Wake-up Function Enable Bit: 0 = Enable IRQ for main system oscillator wake-up function 1 = Disable IRQ for main system oscillator wake-up function
Not used
Divide-by selection bits for CPU clock frequency: 00 = fxx/16 01 = fxx/8 10 = fxx/2 11 = fxx/1 (non-divided)
Figure 7-2. System Clock Control Register (CLKCON)
STOP Control Register (STPCON) D7H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
STOP Control bits: Other values = Disable STOP instruction 10100101 = Enable STOP instruction
Figure 7-3. STOP Control Register (STPCON)
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S3C9498/F9498
RESET and POWER-DOWN
8
OVERVIEW
RESET and POWER-DOWN
SYSTEM RESET
During a power-on Reset, the voltage at VDD goes to High level and the nRESET pin is forced to Low level. The RESET signal is input through a Schmitt trigger circuit where it is then synchronized with the CPU clock. This procedure brings S3C9498/F9498 into a known operating status. To allow time for internal CPU clock oscillation to stabilize, the nRESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance. The minimum required oscillation stabilization time for a Reset operation is 1millisecond. Whenever a reset occurs during normal operation (that is, when both VDD and nRESET are High level), the nRESET pin is forced Low and the reset operation starts. All system and peripheral control registers are then Reset to their default hardware values. In summary, the following sequence of events occurs during a reset operation: -- Interrupt is disabled. -- The watchdog function is enabled. -- Ports 0-3 are set to input mode. -- Peripheral control and data registers are disabled and reset to their default hardware values. -- The program counter (PC) is loaded with the program reset address in the ROM, 0100H. -- When the programmed oscillation stabilization time interval has elapsed, the instruction stored in ROM location 0100H (and 0101H) is fetched and executed.
NORMAL MODE RESET OPERATION In normal (masked ROM) mode, the Test pin is tied to VSS. A reset enables access to the 8 on-chip ROM. (The external interface is not automatically configured).
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RESET and POWER-DOWN
S3C9498/F9498
HARDWARE RESET VALUES The reset values for CPU and system registers, peripheral control registers, and peripheral data registers following a reset operation. The following notation is used to represent reset values: -- A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively. -- An "x" means that the bit value is undefined after a reset. -- A dash ("-") means that the bit is either not used or not mapped, but read 0 is the bit value.
Table 8-1. S3C9498/F9498Registers Values after RESET (Continued) Register Name Timer C control register Timer D control register Timer C data register register Timer D data register register System Clock control register System flags register UART Baud rate data register STOP control register Timer Counter selection register Stack pointer register Timer counter register Basic timer control register Basic timer counter register System mode register Mnemonic TCCON TDCON TCDATA TDDATA CLKCON FLAGS BRDATA STPCON TCNTSEL SP TCNT BTCON BTCNT SYM Address Dec 208 209 210 211 212 213 214 215 216 217 218 220 221 223 Hex D0H D1H D2H D3H D4H D5H D6H D7H D8H D9H DAH DCH DDH DFH 7 0 0 1 1 0 x 1 0 - x x 0 0 - 6 0 0 1 1 - x 1 0 - x x 0 0 - Bit Values After RESET 5 0 0 1 1 - x 1 0 - x x 0 0 - 4 0 0 1 1 0 x 1 0 - x x 0 0 - 3 0 0 1 1 0 - 1 0 - x x 0 0 0 2 0 0 1 1 - - 1 0 0 x x 0 0 0 1 0 0 1 1 - - 1 0 0 x x 0 0 0 0 0 0 1 1 - - 1 0 0 x x 0 0 0
Location DBH is not mapped
Location DEH is not mapped
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S3C9498/F9498
RESET and POWER-DOWN
Table 8-2. S3C9498/F9498Registers Values after RESET (Concluded) Register Name Port 0 Data Register Port 1 Data Register Port 2 Data Register Port 3 Data Register PWM data register PWM Extension data register Port 0 control register P1 interrupt control register Port 1 control High register Port 1 control Low register Port 2 control High register Port 2 control Low register Port 3 control register PWM control register Timer 1 data register(high byte) Timer 1 data register(low byte) Timer 1 control register Serial I/O control register Timer Interrupt pending register Timer A control register SIO pre-scalar register Timer A data register Timer B data register Timer B control register SIO data register A/D converter data register(high byte) A/D converter data register(low byte) A/D converter control register UART control register UART pending register UART data register Mnemonic P0 P1 P2 P3 PWMDATA PWMEX P0CON P1INT P1CONH P1CONL P2CONH P2CONL P3CON PWMCON T1DATAH T1DATAL T1CON SIOCON TINTPND TACON SIOPS TADATA TBDATA TBCON SIODATA ADDATAH ADDATAL ADCON UARTCON UARTPND UDATA Address Dec 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 248 249 250 251 252 253 254 255 Hex E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH EBH ECH EDH EEH EFH F0H F1H F2H F3H F4H F5H F6H F8H F9H FAH FBH FCH FDH FEH FFH 7 0 0 0 0 - 1 - - 0 0 0 0 0 0 1 1 0 0 - 0 0 0 0 0 0 x - 0 0 - x 6 0 0 0 0 - 1 - - 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 x - 0 0 - x Bit Values After RESET 5 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 - 0 x - 0 0 - x 4 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 x - 0 0 - x 3 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 x - 0 0 - x 2 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 x - 0 0 - x 1 0 0 0 0 1 - 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 x x 0 0 0 x 0 0 0 0 0 1 - 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 x x 0 0 0 x
Location F7H is not mapped
NOTE: - : Not mapped or not used, x: Undefined.
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RESET and POWER-DOWN
S3C9498/F9498
POWER-DOWN MODES
STOP MODE Stop mode is invoked by the instruction STOP (opcode 7FH). In Stop mode, the operation of the CPU and all peripherals is halted. That is, the on-chip main oscillator stops and the supply current is reduced to less than 3 A. All system functions stop when the clock "freezes," but data stored in the internal register file is retained. Stop mode can be released in one of two ways: by a reset or by interrupts. NOTE Do not use stop mode if you are using an external clock source because XIN input must be restricted internally to VSS to reduce current leakage. Using RESET to Release Stop Mode Stop mode is released when the nRESET signal is released and returns to high level: all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained. A reset operation automatically selects a slow clock (1/16) because CLKCON.3 and CLKCON.4 are cleared to '00B'. After the programmed oscillation stabilization interval has elapsed, the CPU starts the system initialization routine by fetching the program instruction stored in ROM location 0100H (and 0101H). Using an External Interrupt to Release Stop Mode External interrupts with an RC-delay noise filter circuit can be used to release Stop mode. Which interrupt you can use to release Stop mode in a given situation depends on the microcontroller's current internal operating mode. The external interrupts in the S3C9498/F9498interrupt structure that can be used to release Stop mode are: -- External interrupts P1.0-P1.1 (INT0-INT1) Please note the following conditions for Stop mode release: -- If you release Stop mode using an external interrupt, the current values in system and peripheral control registers are unchanged except STPCON register. -- If you use an external interrupt for Stop mode release, you can also program the duration of the oscillation stabilization interval. To do this, you must make the appropriate control and clock settings before entering Stop mode. -- When the Stop mode is released by external interrupt, the CLKCON.4 and CLKCON.3 bit-pair setting remains unchanged and the currently selected clock value is used. -- The external interrupt is serviced when the Stop mode release occurs. Following the IRET from the service routine, the instruction immediately following the one that initiated Stop mode is executed.
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S3C9498/F9498
RESET and POWER-DOWN
IDLE MODE Idle mode is invoked by the instruction IDLE (opcode 6FH). In idle mode, CPU operations are halted while some peripherals remain active. During idle mode, the internal clock signal is gated away from the CPU, but all peripherals timers remain active. Port pins retain the mode (input or output) they had at the time idle mode was entered. There are two ways to release idle mode: 1. Execute a reset. All system and peripheral control registers are reset to their default values and the contents of all data registers are retained. The reset automatically selects the slow clock fxx/16 because CLKCON.4 and CLKCON.3 are cleared to `00B'. If interrupts are masked, a reset is the only way to release idle mode. 2. Activate any enabled interrupt, causing idle mode to be released. When you use an interrupt to release idle mode, the CLKCON.4 and CLKCON.3 register values remain unchanged, and the currently selected clock value is used. The interrupt is then serviced. When the return-from-interrupt (IRET) occurs, the instruction immediately following the one that initiated idle mode is executed.
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S3C9498/F9498
NOTES
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S3C9498/F9498
I/O PORTS
9
OVERVIEW
Port 0 1 2 3
I/O PORTS
The S3C9498/F9498 microcontroller has four bit-programmable I/O ports, P0-P3. The port 0 and 3 are 3-bit /7-bits ports and the others are 8-bit ports. This gives a total of 22/24/26 I/O pins. Each port can be flexibly configured to meet application design requirements. The CPU accesses ports by directly writing or reading port registers. No special I/O instructions are required. Table 9-1 gives you a general overview of the S3C9498/F9498 I/O port functions. Table 9-1. S3C9498/F9498 Port Configuration Overview Configuration Options I/O port with bit-programmable pins. Configurable to input or push-pull output mode. Pull-up resistors can be assigned by software. Pins can also be assigned individually as alternative function pins. I/O port with bit-programmable pins. Configurable to input or push-pull output mode. Pull-up resistors can be assigned by software. Pins can also be assigned individually as alternative function pins. I/O port with bit-programmable pins. Configurable to input mode, push-pull output mode. Pins can also be assigned individually as alternative function pins. I/O port with bit-programmable pins. Configurable to input mode, push-pull output mode. Pins can also be assigned individually as alternative function pins.
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I/O PORTS
S3C9498/F9498
PORT DATA REGISTERS Table 9-2 gives you an overview of the register locations of all five S3C9498/F9498I/O port data registers. Data registers for ports 0, 1, 2, and 3 have the general format shown in Figure 9-1. Table 9-2. Port Data Register Summary Register Name Port 0 data register Port 1 data register Port 2 data register Port 3 data register Mnemonic P0 P1 P2 P3 Decimal 224 225 226 227 Hex E0H E1H E2H E3H R/W R/W R/W R/W R/W
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S3C9498/F9498
I/O PORTS
PORT 0 Port 0 is a 3-bit I/O Port that you can use two ways: -- General-purpose I/O -- Alternative function Port 0 is accessed directly by writing or reading the port 0 data register, P0 at location E0H. Port 0 Control Register (P0CON) Port 0 pins are configured individually by bit-pair settings in three control registers located : P0CON. When you select output mode, a push-pull or an open-drain circuit is configured. In input mode, many different selections are available: -- Input mode. -- Output mode(Push-pull or Open-drain) -- Alternative function: UART module - TXD/RXD -- Alternative function: RESETB
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I/O PORTS
S3C9498/F9498
Port 0 Control Register (P0CON) E6H, R/W, Reset value:00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
P0.2
P0.1 /TxD
P0.0 /RxD
.7 .6 bit XX Not used for 9498
.5 .4 bit/P0.2 00 01 10 11 Input mode with pull-up Input mode Push-pull output Open-drain Output
.3 .2 bit/P0.1/TxD 00 01 10 11 Input mode with pull-up Input mode Push-pull output Alternative function: TxD Output
.1 .0 bit/P0.0/RxD 00 01 10 11 NOTE: Input mode with pull-up; RxD output Input mode; RxD output Push-pull output Alternative function: RxD output
When users use Port 0, users must be care of the pull-up resistance status register value.
Figure 9-1. Port 0 High-Byte Control Register (P0CON)
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S3C9498/F9498
I/O PORTS
PORT 1 Port 1 is an 8-bit I/O port that you can use two ways: -- General-purpose I/O -- Alternative function Port 1 is accessed directly by writing or reading the port 1 data register, P1 at location E1H. Port 1 Control Register (P1CONH, P1CONL) Port 1 pins are configured individually by bit-pair settings in three control registers located: P1CONL(low byte, E9H) and P1CONH(high byte, E8H). When you select output mode, a push-pull circuit is configured. In input mode, many different selections are available: -- Input mode. -- Push-pull output mode -- Alternative function: External Interrupt - INT0, INT1 -- Alternative function: Timer D output- TDOUT -- Alternative function: ADC input mode - ADC0, ADC1, ADC2, ADC3, ADC4, ADC5, ADC6, ADC7
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I/O PORTS
S3C9498/F9498
Port 1 Control Register, High Byte (P1CONH) E8H, R/W, Reset value:00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P1.7 /ADC7 .7 .6 bit/P1.7/ADC7 00 01 10 11
P1.6 /ADC6 /TDOUT
P1.5 /ADC5
P1.4 /ADC4
Input mode with pull-up Not used for S3F9498 Push-pull output Alternative function: ADC7 input
.5 .4 bit/P1.6/ADC6 00 01 10 11 Input mode with pull-up Alternative function: TDOUT mode Push-pull output Alternative function: ADC6 input
.3 .2 bit/P1.5/ADC5 00 01 10 11 Input mode with pull-up Input mode Push-pull output Alternative function: ADC5 input
.1 .0 bit/P1.4/ADC4 00 01 10 11 Input mode with pull-up Input mode Push-pull output Alternative function: ADC4 input
Figure 9-2. Port 1 High-Byte Control Register (P1CONH)
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S3C9498/F9498
I/O PORTS
Port 1 Control Register, Low Byte (P1CONL) E9H, R/W, Reset value:00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P1.3 /ADC3 .7 .6 bit/P1.3/ADC3 00 01 10 11
P1.2 /ADC2
P1.1 /ADC1 /INT1
P1.0 /ADC0 /INT0
Input mode with pull-up Input mode Push-pull output Alternative function: ADC3 input
.5 .4 bit/P1.2/ADC2 00 01 10 11 Input mode with pull-up Input mode Push-pull output Alternative function: ADC2 input
.3 .2 bit/P1.1/ADC1/INT1 00 01 10 11 Input mode with pull-up; INT1 input Input mode; INT1 input Push-pull output Alternative function: ADC1 input
.1 .0 bit/P1.0/ADC0/INT0 00 01 10 11 Input mode with pull-up; INT0 input Input mode; INT0 input Push-pull output Alternative function: ADC0 input
Figure 9-3. Port 1 Low-Byte Control Register (P1CONL)
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I/O PORTS
S3C9498/F9498
Port 1 External Interrupt Register (P1INT) E7H, R/W, Reset value:00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
INT1
INT0
INT1 INT0
.7 .6 bits Not used for S3F9498 .5 .4 bits INT1 Interrupt Enable/Disable Selection 0x 10 11 0x 10 11 Interrupt disable Interrupt enable; falling edge Interrupt enable; rising edge Interrupt disable Interrupt enable; falling edge Interrupt enable; rising edge
.3 .2 bits INT0 Interrupt Enable/Disable Selection
.1 bits INT1 Pending bit 0 1 0 1 No interrupt Pending (clear pending bit when write) Interrupt enable No interrupt Pending (clear pending bit when write) Interrupt enable
.0 bits INT0 Pending bit
Figure 9-4. Port 1 Interrupt Control Register P1PND)
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S3C9498/F9498
I/O PORTS
PORT 2 Port 2 is an 8-bit I/O port that you can use two ways: -- General-purpose I/O -- Alternative function Port 2 is accessed directly by writing or reading the port 2 data register, P2 at location E2H. Port 2 Control Register (P2CONH, P2CONL) Port 2 pins are configured individually by bit-pair settings in two control registers located : P2CONL (low byte, EBH) and P2CONH (high byte, EAH). When you select output mode, a push-pull, an open-drain circuit is configured. In input mode, many different selections are available: -- Input mode. -- Output mode(Push-pull or Open-drain) -- Alternative function: Timer A signal in/out mode - TAOUT, TACAP, TACK -- Alternative function: Timer B signal out mode - TBOUT -- Alternative function: Timer 1 signal in/out mode - T1OUT, T1CAP, T1CK -- Alternative function: PWM out mode - PWM
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I/O PORTS
S3C9498/F9498
Port 2 Control Register, High Byte (P2CONH) EAH, R/W, Reset value:00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P2.7 /PWM .7 .6 bit/P2.7/PWM 00 01 10 11
P2.6 /T1CAP
P2.5 /T1OUT
P2.4 /T1CK
Input mode with pull-up Input mode Push-pull output Alternative function: PWM signal output
.5 .4 bit/P2.6/T1CAP 00 01 10 11 Input mode with pull-up; T1CAP input Input mode; T1CAP input Push-pull output Open-drain output
.3 .2 bit/P2.5/T1OUT 00 01 10 11 Input mode with pull-up Input mode Push-pull output Alternative function: T1OUT signal output
.1 .0 bit/P2.4/T1CK 00 01 10 11 Input mode with pull-up; T1CK input Input mode;T1CK input Push-pull output Open-drain output
Figure 9-5. Port 2 High-Byte Control Register (P2CONH)
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S3C9498/F9498
I/O PORTS
Port 2 Control Register, Low Byte (P2CONL) EBH, R/W, Reset value:00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P2.3 /TBOUT
P2.2 /TACAP
P2.1 /TACK
P2.0 /TAOUT
.7 .6 bit/P2.3/TBOUT 00 01 10 11 Input mode with pull-up Input mode Push-pull output Alternative function: TBOUT signal output
.5 .4 bit/P2.2/TACAP 00 01 10 11 Input mode with pull-up; TACAP input Input mode; TACAP input Push-pull output Open-drain output
.3 .2 bit/P2.1/TACK 00 01 10 11 Input mode with pull-up; TACK input Input mode; TACK input Push-pull output Open-drain output
.1 .0 bit/P2.0/TAOUT 00 01 10 11 Input mode with pull-up Input mode Push-pull output Alternative function: TAOUT signal output
Figure 9-6. Port 2 Low-Byte Control Register (P2CONL)
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I/O PORTS
S3C9498/F9498
PORT 3 Port 3 is a 7-bit I/O Port that you can use two ways: -- General-purpose I/O -- Alternative function Port 3 is accessed directly by writing or reading the port 3 data register, P3 at location E3H. Port 3 Control / Interrupt Control Register (P3CON) Port 3 pins are configured individually by bit-pair settings in two control registers located : P3CON (ECH). When you select output mode, a push-pull or an open-drain circuit is configured. In input mode, many different selections are available: -- Input mode. -- Output mode(Push-pull or Open-drain) -- Alternative function: SIO module - SI/SO/SCK
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S3C9498/F9498
I/O PORTS
Port 3 Control Register (P3CON) ECH, R/W, Reset value:00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P3.6/P3.5 P3.4/P3.3 00 01 10 11
P3.2 / SCK
P3.1 / SO
P3.2 / SI
.7 .6 bit/P3.6/P3.5/P3.4/P3.3 Input mode with pull-up Input mode Push-pull output Open-drain output
.5 .4 bit/P3.2/SCK 00 01 10 11 Input mode, pull-up (SCK input) Input mode(SCK input) Push-pull output Alternative output mode (SCK output)
.5 .4 bit/P3.1/SO Input mode, pull-up 00 Input mode 01 10 Push-pull output 11 Alternative output mode (SO) .5 .4 bit/P3.0/SI 00 01 10 11 Input mode, pull-up (SI) Input mode(SI) Push-pull output Open-drain output mode
Figure 9-7. Port 3 High-Byte Control Register (P3CON)
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I/O PORTS
S3C9498/F9498
NOTES
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S3C9498/F9498
BASIC TIMER
10
OVERVIEW
Basic Timer (BT)
BASIC TIMER
You can use the basic timer (BT) in two different ways: -- As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. -- To signal the end of the required oscillation stabilization interval after a reset or a Stop mode release. The functional components of the basic timer block are: -- Clock frequency divider (fOSC divided by 4096, 1024, or 128) with multiplexer -- 8-bit basic timer counter, BTCNT (DDH, read-only) -- Basic timer control register, BTCON (DCH, read/write)
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BASIC TIMER
S3C9498/F9498
BASIC TIMER (BT)
BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. A reset clears BTCON to "00H". This enables the watchdog function and selects a basic timer clock frequency of fOSC/4096. To disable the watchdog function, you must write the signature code "1010B" to the basic timer register control bits BTCON.7-BTCON.4. The 8-bit basic timer counter, BTCNT, can be cleared during normal operation by writing a "1" to BTCON.1. To clear the frequency dividers for the basic timer input clock, you write a "1" to BTCON.0.
Basic Timer Control Register (BTCON) DCH, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Watchdog timer enable bits: 1010B = Disable watchdog function Other value = Enable watchdog function
Divider clear bit for basic timer 0 = No effect 1 = Clear both dividers Basic timer counter clear bits: 0 = No effect 1 = Clear basic timer counter
Basic timer input clock selection bits: 00 = fosc/4096 01 = fosc/1024 10 = fosc/128 11 = Invalid selection NOTE: When you write a 1 to BTCON.0 (or BTCON.1), the basic timer divider (or basic timer counter) is cleared. The bit is then cleared automatically to 0.
Figure 10-1. Basic Timer Control Register (BTCON)
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S3C9498/F9498
BASIC TIMER
BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7-BTCON.4 to any value other than "1010B" (The "1010B" value disables the watchdog function). A reset clears BTCON to "00H", automatically enabling the watchdog timer function. A reset also selects the oscillator clock divided by 4096 as the BT clock. A reset whenever a basic timer counter overflow occurs. During normal operation, the application program must prevent the overflow, and the accompanying reset operation, from occurring. To do this, the BTCNT value must be cleared (by writing a "1" to BTCON.1) at regular intervals. If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation will not be executed and a basic timer overflow will occur, initiating a reset. In other words, during normal operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always broken by a BTCNT clear instruction. If a malfunction does occur, a reset is triggered automatically. Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when Stop mode has been released by an external interrupt. In Stop mode, whenever a reset or an external interrupt occurs, the oscillator starts. The BTCNT value then starts increasing at the rate of fOSC/4096 (for reset), or at the rate of the preset clock source (for an external interrupt). When BTCNT.4 is set, a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal operation. In summary, the following events occur when Stop mode is released: 1. During Stop mode, an external power-on reset or an external interrupt occurs to trigger the Stop mode release and oscillation starts. 2. If an external power-on reset occurred, the basic timer counter will increase at the rate of fOSC/4096. If an external interrupt is used to release Stop mode, the BTCNT value increases at the rate of the preset clock source. 3. Clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter is set. 4. When a BTCNT.4 is set, normal CPU operation resumes. Figure 10-2 and 10-3 shows the oscillation stabilization time on RESET and STOP mode release
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BASIC TIMER
S3C9498/F9498
Oscillation Stabilization Time
Normal Operating mode
0.8 VDD VDD Reset Release Voltage nRESET trst ~ RC Internal Reset Release
0.8 VDD
Oscillator (XOUT) Oscillator Stabilization Time
BTCNT clock BTCNT value 10000B 00000B tWAIT = (4096x16)/fOSC
Basic timer increment and CPU operations are IDLE mode
NOTE: Duration of the oscillator stabilization wait time, tWAIT, when it is released by a Power-on-reset is 4096 x 16/fOSC. ~ tRST ~RC (R and C are value of external power on reset)
Figure 10-2. Oscillation Stabilization Time on RESET
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S3C9498/F9498
BASIC TIMER
Normal Operating Mode VDD STOP Instruction Execution External Interrupt RESET STOP Release Signal
STOP Mode
Oscillation Stabilization Time
Normal Operating Mode
STOP Mode Release Signal
Oscillator (XOUT)
BTCNT clock
10000B BTCNT Value 00000B tWAIT Basic Timer Increment NOTE: Duration of the oscillator stabilzation wait time, tWAIT, it is released by an interrupt is determined by the setting in basic timer control register, BTCON.
BTCON.3 0 0 1 1
BTCON.2 0 1 0 1
tWAIT (4096 x 16)/fosc (1024 x 16)/fosc (128 x 16)/fosc Invalid setting
tWAIT (When fOSC is 8 MHz) 8.19 ms 2.05 ms 0.25 ms
Figure 10-3. Oscillation Stabilization Time on STOP Mode Release
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BASIC TIMER
S3C9498/F9498
F PROGRAMMING TIP -- Configuring the Basic Timer
This example shows how to configure the basic timer to sample specification. ORG VECTOR 0000H 00H,INT_9498 ; S3C9498/F9498 has only one interrupt vector
;--------------<< Smart Option >> ORG DB DB DB DB 003CH 0FFH 0FFH 0C7H 0FFH ; ; ; ; 003CH, must be initialized to 1 003DH, must be initialized to 1 003EH, enable LVR (3.0 V) 003FH, RESET pin enable
;--------------<< Initialize System and Peripherals >> ORG RESET: DI LD LD
* *
0100H CLKCON,#00011000B SP,#0C0H ; Disable interrupt ; Select non-divided CPU clock ; Stack pointer must be set
LD
BTCON,#02H
; Enable watchdog function ; Basic timer clock: fOSC/4096 ; Basic counter (BTCNT) clear
* * *
EI ;--------------<< Main loop >> MAIN:
*
; Enable interrupt
LD
* * *
BTCON,#02H
; Enable watchdog function ; Basic counter (BTCNT) clear
JR
T,MAIN
;
;--------------<< Interrupt Service Routines >> INT_9498:
* * *
IRET
* *
; Interrupt enable bit and pending bit check ; ; Pending bit clear ;
END
;
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S3C9498/F9498
8-BIT TIMER A/B
11
8-BIT TIMER A
OVERVIEW
8-BIT TIMER A/B
The 8-bit timer A is an 8-bit general-purpose timer/counter. Timer A has three operating modes, you can select one of them using the appropriate TACON setting: -- Interval timer mode (Toggle output at TAOUT pin) -- Capture input mode with a rising or falling edge trigger at the TACAP pin -- PWM mode (TAOUT) Timer A has the following functional components: -- Clock frequency divider (fxx divided by 1024, 256, or 64) with multiplexer -- External clock input pin (TACK) -- 8-bit counter (TACNT), 8-bit comparator, and 8-bit reference data register (TADATA) -- I/O pins for capture input (TACAP) or PWM or match output (TAOUT) -- Timer A overflow interrupt and match/capture interrupt generation -- Timer A control register, TACON (F3H, read/write)
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8-BIT TIMER A/B
S3C9498/F9498
FUNCTION DESCRIPTION Timer A Interrupts The timer A module can generate two interrupts: the timer A overflow interrupt (TAOVF), and the timer A match/ capture interrupt (TAINT). Timer A overflow interrupt and match/capture interrupt pending conditions are cleared by software when it has been serviced. Interval Timer Function The timer A module can generate an interrupt: the timer A match interrupt (TAINT). When timer A interrupt occurs and is serviced by the CPU, the pending condition is cleared by software. In interval timer mode, a match signal is generated and TAOUT is toggled when the counter value is identical to the value written to the Timer A reference data register, TADATA. The match signal generates a timer A match interrupt and clears the counter. If, for example, you write the value 10H to TADATA and 0AH to TACON, the counter will increment until it reaches 10H. At this point, the TA interrupt request is generated, the counter value is reset, and counting resumes. Pulse Width Modulation Mode Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the TAOUT pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer A data register. In PWM mode, however, the match signal does not clear the counter. Instead, it runs continuously, overflowing at FFH, and then continues incrementing from 00H. Although you can use the match signal to generate a timer A overflow interrupt, interrupts are not typically used in PWM-type applications. Instead, the pulse at the TAOUT pin is held to Low level as long as the reference data value is less than or equal to ( ) the counter value and then the pulse is held to High level for as long as the data value is greater than ( > ) the counter value. One pulse width is equal to tCLK * 256 . Capture Mode In capture mode, a signal edge that is detected at the TACAP pin opens a gate and loads the current counter value into the Timer A data register. You can select rising or falling edges to trigger this operation. Timer A also gives you capture input source: the signal edge at the TACAP pin. You select the capture input by setting the value of the timer A capture input selection bit in the Port 2 low-byte control register, P2CONL, (EBH). When P2CONL.5.4 is 00 and 01, the TACAP input or normal input is selected. When P2CONL.5.4 is set to 10 and 11, output is selected. Both kinds of timer A interrupts can be used in capture mode: the timer A overflow interrupt is generated whenever a counter overflow occurs; the timer A match/capture interrupt is generated whenever the counter value is loaded into the Timer A data register. By reading the captured data value in TADATA, and assuming a specific value for the timer A clock frequency, you can calculate the pulse width (duration) of the signal that is being input at the TACAP pin.
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S3C9498/F9498
8-BIT TIMER A/B
TIMER A CONTROL REGISTER (TACON) You use the timer A control register, TACON -- Select the timer A operating mode (interval timer, capture mode and PWM mode) -- Select the timer A input clock frequency -- Clear the timer A counter, TACNT -- Enable the timer A overflow interrupt or timer A match/capture interrupt -- Timer A start/stop -- Clear Timer A match/capture interrupt pending conditions TACON is located at address F3H, and is read/write addressable using Register addressing mode. A reset clears TACON to '00H'. This sets timer A to normal interval timer mode, selects an input clock frequency of fxx/1024, and disables all Timer A interrupts. You can clear the timer A counter at any time during normal operation by writing a "1" to TACON.3. You can start Timer A counter by writing a "1" to TACON.0. The timer A overflow interrupt (TAOVF) has the vector address 00H-01H. When a timer A overflow interrupt occurs and is serviced by the CPU, but the pending condition must clear by software. To enable the timer A match/capture interrupt , you must write TACON.1 to "1". To generate the exact time interval, you should write TACON.3 and TINTPND .0, which cleared counter and interrupt pending bit. When interrupt service routine is served, the pending condition must be cleared by software by writing a `0' to the interrupt pending bit.
Timer A Control Register (TACON) F3H, R/W, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Timer A input clock selection bit: 00 = fxx/1024 01 = fxx/256 10 = fxx/64 11 = External clock (TACK) Timer A operating mode selection bit: 00 = Interval mode (TAOUT mode) 01 = Capture mode (capture on rising edge, counter running, OVF can occur) 10 = Capture mode (capture on falling edge, counter running, OVF can occur) 11 = PWM mode (OVF interrupt and match interrupt can occur)
Timer A start/stop bit: 0 = Stop timer A 1 = Start timer A Timer A match/capture interrupt enable bit: 0 = Disable interrupt 1 = Enable interrrupt Timer A overflow interrupt enable bit: 0 = Disable overflow interrupt 1 = Enable overflow interrrupt
Timer A counter clear bit: 0 = No effect 1 = Clear the timer A counter (when write) NOTE: When the counter clear bit(.3) is set, the 8-bit counter is cleared and it also is cleared automatically.
Figure 11-1. Timer A Control Register (TACON)
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8-BIT TIMER A/B
S3C9498/F9498
Timer Interrupt Pending Register (TINTPND) F2H, Reset: 00H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Timer 1 overflow interrupt pending flag: 0 = Not pending (clear pending bit) 1 = Interrupt pending Timer 1 match interrupt pending flag: 0 = Not pending (clear pending bit) 1 = Interrupt pending Timer D overflow interrupt pending flag: 0 = Not pending (clear pending bit) 1 = Interrupt pending Timer D macth/capture interrupt pending flag: 0 = Not pending (clear pending bit) 1 = Interrupt pending
Timer A macth/capture interrupt pending flag: 0 = Not pending (clear pending bit) 1 = Interrupt pending Timer A overflow interrupt pending flag: 0 = Not pending (clear pending bit) 1 = Interrupt pending Timer B match/capture interrupt pending flag: 0 = Not pending (clear pending bit) 1 = Interrupt pending Timer B overflow interrupt pending flag: 0 = Not pending (clear pending bit) 1 = Interrupt pending
Figure 11-2. Timer interrupts Pending Register (TINTPND)
Timer A Data Register (TADATA) F5H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Reset Value: FFh
Figure 11-3. Timer A DATA Register (TADATA)
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S3C9498/F9498
8-BIT TIMER A/B
BLOCK DIAGRAM
TACON.2 TACON.7-.6 fxx/1024 fxx/256 fxx/64 TACK Match M U X TACON.1 Pending M U X Overflow Data Bus 8 8-bitUp-Counter (Read Only) Clear Pending TINTPND.1
TAOVF
TACON.3
8-bit Comparator M U X
TAINT
TACAP
TINTPND.0 M U X TAOUT
TimerA BufferReg
TACON.5.4 Timer A Data Register (Read/Write) 8 Data Bus NOTES: 1. When PWM mode, match signal cannot clear counter. 2. Pending bit is located at TINTPND register.
TACON.5.4
Figure 11-4. Timer A Functional Block Diagram
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8-BIT TIMER A/B
S3C9498/F9498
8-BIT TIMER B
OVERVIEW The S3C9498/F9498 micro-controller has an 8-bit counter called timer B.
TBCON.2 TBCON.7-.6 fxx/8 fxx/4 fxx/2 fxx Match M U X Overflow Data Bus 8 8-bit Up-Counter (Read Only) Clear Pending TINTPND.3
TBOVF
TBCON.3
TBCON.1 8-bit Comparator Pending TINTPND.2 Timer B Buffer Reg
TBINT
TBOUT
Timer B Data Register (Read/Write) 8 Data Bus NOTES: 1. When PWM mode, match signal cannot clear counter. 2. Pending bit is located at TINTPND register.
Figure 11-5. Timer B Functional Block Diagram
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S3C9498/F9498
8-BIT TIMER A/B
Timer B Control Register (TBCON) F8H, R/W, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Timer B input clock selection bit: 00 = fxx/8 01 = fxx/4 10 = fxx/2 11 = fxx/1 Not used
Timer B start/stop bit: 0 = Stop timer B 1 = Start timer B Timer B match interrupt enable bit: 0 = Disable interrupt 1 = Enable interrrupt Timer B overflow interrupt enable bit: 0 = Disable overflow interrupt 1 = Enable overflow interrrupt
Timer B operating mode selection bit: 0 = Interval mode (TBOUT mode) 1 = PWM mode (OVF interrupt and match interrupt can occur)
Timer B counter clear bit: 0 = No effect 1 = Clear the timer B counter (when write) NOTE: When th counter clear bit(.3) is set, the 8-bit counter is cleared and it also is cleared automatically.
Figure 11-6. Timer B Control Register (TBCON)
Timer B Data Register (TBDATA) F6H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Reset Value: FFh
Figure 11-7. Timer B DATA Registers (TBDATA)
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8-BIT TIMER A/B
S3C9498/F9498
NOTES
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S3C9498/F9498
16-BIT TIMER 1
12
OVERVIEW
16-BIT TIMER 1
The S3C9498/F9498 has two 16-bit timer/counters. The 16-bit timer 1 is a 16-bit general-purpose timer/counter. Timer 1 has three operating modes, one of which you select using the appropriate T1CON setting is: -- Interval timer mode (Toggle output at T1OUTpin) -- Capture input mode with a rising or falling edge trigger at the T1CAP pin -- PWM mode (T1PWM); PWM output shares their output port with T1OUT pin Timer 1 has the following functional components: -- Clock frequency divider (fxx divided by 1024, 256, 64, 8, 1 or T1CK: External clock) with multiplexer -- External clock input pin (T1CK ) -- A 16-bit counter , 16-bit comparator, and two 16-bit reference data register (T1DATAH/L) -- I/O pins for capture input (T1CAP), or match output (T1OUT) -- Timer 1 overflow interrupt and match/capture interrupt generation -- Timer 1 control register, T1CON
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16-BIT TIMER 1
S3C9498/F9498
FUNCTION DESCRIPTION Timer 1 Interrupts The timer 1 module can generate two interrupts, the timer 1 overflow interrupt (T1OVF), and the timer 1 match/capture interrupt (T1INT). A timer 1 overflow interrupt pending condition is cleared by software when it has been serviced. A timer 1 match/capture interrupt, T1INT pending condition is also cleared by software when it has been serviced. Interval Mode (match) Timer 1 module can generate an interrupt: Timer 1 match interrupt (T1INT). In interval timer mode, a match signal is generated and T1OUT is toggled when the counter value is identical to the value written to the T1 reference data register, T1DATAH/L. The match signal generates a timer 1 match interrupt (T1INT) and clears the counter. Capture Mode In capture mode for Timer 1, a signal edge that is detected at the T1CAP pin opens a gate and loads the current counter value into the T1 data register (T1DATAH/L for rising edge, or falling edge). You can select rising or falling edges to trigger this operation. Timer 1 also gives you capture input source, the signal edge at the T1CAP pin. You select the capture input by setting the capture input selection bit in the port 2 control register, P2CONH,. Both kinds of timer 1 interrupts (T1OVF, T1INT) can be used in capture mode, the timer 1 overflow interrupt is generated whenever a counter overflow occurs, the timer 1 capture interrupt is generated whenever the counter value is loaded into the T1 data register (T1DATAH/L). By reading the captured data value in T1DATAH/L, and assuming a specific value for the timer 1 clock frequency, you can calculate the pulse width (duration) of the signal that is being input at the T1CAP pin. PWM Mode Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the T1OUT pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 1 data register. In PWM mode, however, the match signal does not clear the counter but can generate a match interrupt. The counter runs continuously, overflowing at FFFFH, and then continuous increasing from 0000H. Whenever an overflow is occurred, an overflow (OVF1) interrupt can be generated. Although you can use the match or the overflow interrupt in the PWM mode, these interrupts are not typically used in PWM-type applications. Instead, the pulse at the T1OUT pin is held to low level as long as the reference data value is less than or equal to() the counter value and then the pulse is held to high level for as long as the data value is greater than(>) the counter value. One pulse width is equal to tCLK .
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S3C9498/F9498
16-BIT TIMER 1
TIMER 1 CONTROL REGISTER (T1CON) You use the TIMER 1 control register, T1CON, to -- Select the TIMER 1 operating mode (interval timer, capture mode, or PWM mode) -- Select the TIMER 1 input clock frequency -- Clear the TIMER 1 counter. -- Enable the TIMER 1 overflow interrupt -- Enable the TIMER 1 match/capture interrupt T1CON is located at address F0H, and is read/write addressable using Register addressing mode. A reset clears T1CON to `00H'. This sets TIMER 1 to normal interval timer mode, selects an input clock frequency of fxx/1024, and disables all TIMER 1 interrupts. You can clear the TIMER 1 counter at any time during normal operation by writing a "1" to T1CON.2. To generate the exact time interval, you should write "1" to T1CON.2 and clear appropriate pending bits of the TINTPND.6 register. To detect a match/capture or overflow interrupt pending condition when T1INT or T1OVF is disabled, the application program should poll the pending bit T1CON and INTPND register. When a "1" is detected, a TIMER 1 match/capture or overflow interrupt is pending. When the sub-routine has been serviced, the pending condition must be cleared by software by writing a "0" to the interrupt pending bit.
Timer 1 Control Register (T1CON) F0H, R/W, Reset Value = 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Timer 1 clock source selection bit: 000 = fxx/1024 001 = fxx 010 = fxx/256 011 = External clock(T1CK) falling edge 100 = fxx/64 101 = External clock(T1CK) rising edge 110 = fxx/8 111 = Counter stop
Timer 1 overflow interrupt enable bit: 0 = Disable overflow interrupt 1 = Enable overflow interrrupt Timer 1 match/capture interrupt enable bit: 0 = Disable interrupt 1 = Enable interrrupt Timer 1 counter clear bit: 0 = No effect 1 = Clear counter ( uto-clear bit) A
Timer 1 operating mode selection bit: 00 = Interval mode 01 = Capture mode (capture on rising edge, OVF can occur) 10 = Capture mode (capture on falling edge, OVF can occur) 11 = PWM mode (T1OVF and T1INT can occur) NOTE: Interrupt pending bits are located in TINTPND register.
Figure 12-1. TIMER 1 Control Register (T1CON)
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16-BIT TIMER 1
S3C9498/F9498
Timer Interrupt Pending Register (TINTPND) F2H, Reset: 00H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Timer 1 overflow interrupt pending flag: 0 = Not pending (clear pending bit) 1 = Interrupt pending Timer 1 match interrupt pending flag: 0 = Not pending (clear pending bit) 1 = Interrupt pending Timer D overflow interrupt pending flag: 0 = Not pending (clear pending bit) 1 = Interrupt pending Timer D macth/capture interrupt pending flag: 0 = Not pending (clear pending bit) 1 = Interrupt pending
Timer A macth/capture interrupt pending flag: 0 = Not pending (clear pending bit) 1 = Interrupt pending Timer A overflow interrupt pending flag: 0 = Not pending (clear pending bit) 1 = Interrupt pending Timer B match/capture interrupt pending flag: 0 = Not pending (clear pending bit) 1 = Interrupt pending Timer B overflow interrupt pending flag: 0 = Not pending (clear pending bit) 1 = Interrupt pending
Figure 12-2. Timer A/B/D and TIMER 1 Pending Register (TINTPND)
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S3C9498/F9498
16-BIT TIMER 1
BLOCK DIAGRAM
T1CON.7-.5 T1CON.0 fxx/1024 fxx/256 fxx/64 fxx/8 fxx/1 T1CK VSS 16-bit Comparator M U X Match M U X Overflow Data Bus 8 M U X 16-bit Up-Counter (Read Only) Clear Pending TINTPND.7 T1OVF
T1CON.2
T1CON.1 Pending TINTPND.6
T1INT
T1CAP
16-bit Timer Buffer
T1OUT T1PWM
T1CON.4.3 16-bit Timer Data Register (T1DATAH/L) 8 Data Bus NOTES: 1. When PWM mode, match signal cannot clear counter. 2. Pending bit is located at TINTPND register.
T1CON.4.3 PG output signal
Figure 12-3. TIMER 1 Functional Block Diagram
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16-BIT TIMER 1
S3C9498/F9498
F PROGRAMMING TIP -- Using the Timer 1
ORG VECTOR ORG INITIAL: LD LD LD LD LD LD SYM,#00h SP,#0C0H BTCON,#10100011b T1DATAH,#00H T1DATAL,#0F0H T1CON,#01001110b ; fxx/256, interval, clear counter, Enable interrupt ; Duration 7.68ms (8 MHz x'tal) ; Disable Global/Fast interrupt ; Set stack area ; Disable Watch-dog 0000h 00h,INT_9498 0100h
EI MAIN:
* * *
MAIN ROUTINE
* * *
JR INT_9498:
* * *
T,MAIN
Interrupt service routine
* * *
IRET .END
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S3C9498/F9498
TIMER 0
13
OVERVIEW
TIMER 0
ONE 16-BIT TIMER MODE (TIMER 0)
The 16-bit timer 0 is used in one 16-bit timer or two 8-bit timers mode. If TCCON.7 is set to "1", Timer 0 is used as a 16-bit timer. If TCCON.7 is set to "0", timer 0 is used as two 8-bit timers. -- One 16-bit timer mode (Timer 0) -- Two 8-bit timers mode (Timer C and D)
The 16-bit timer 0 is an 16-bit general-purpose timer. Timer 0 has the interval timer mode by using the appropriate TCCON setting. Timer 0 has the following functional components: -- Clock frequency divider (fxx divided by 1024, 512, 8, or 1) with multiplexer -- 16-bit comparator, and 16-bit reference data register (TCDATA, TDDATA) -- Timer 0 match interrupt generation -- Timer 0 control register, TCCON (D0H, read/write) FUNCTION DESCRIPTION Interval Timer Function The timer 0 module can generate an interrupt: the timer 0 match interrupt (T0INT). The T0INT pending condition should be cleared by software when it has been serviced. Even though T0INT is disabled, the application's service routine can detect a pending condition of T0INT by the software and execute it's sub-routine. When this case is used, the T0INT pending bit must be cleared by the application sub-routine by writing a "0" to the TCCON.0 pending bit. In interval timer mode, a match signal is generated when the counter value is identical to the values written to the timer 0 reference data registers, TCDATA and TDDATA. The match signal generates a timer 0 match interrupt and clears the counter. If, for example, you write the value 32H and 10H to TCDATA and TDDATA, respectively, and 8EH to TCCON, the counter will increment until it reaches 3210H. At this point, the timer 0 interrupt request is generated, the counter value is reset, and counting resumes.
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TIMER 0
S3C9498/F9498
Timer 0 Control Register (TCCON) You use the timer 0 control register, TCCON, to -- Enable the timer 0 operating (interval timer) -- Select the timer 0 input clock frequency -- Clear the timer 0 counter -- Enable the timer 0 interrupt -- Clear timer 0 interrupt pending conditions TCCON is located at address D0H, and is read/write addressable using register addressing mode. A reset clears TCCON to "00H". This sets timer 0 to disable interval timer mode, selects an input clock frequency of fxx/1024, and disables timer 0 interrupt. You can clear the timer 0 counter at any time during normal operation by writing a "1" to TCCON.3. To enable the timer 0 interrupt , you must write TCCON.7, TCCON.2, and TCCON.1 to "1". To generate the exact time interval, you should write TCCON.3 and TCCON.0, which cleared counter and interrupt pending bit. To detect an interrupt pending condition when T0INT is disabled, the application program polls pending bit, TCCON.0. When a "1" is detected, a timer 0 interrupt is pending. When the T0INT sub-routine has been serviced, the pending condition must be cleared by software by writing a "0" to the timer 0 interrupt pending bit, TCCON.0.
Timer C Control Register (TCCON) D0H, Reset = 00H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Timer 0 operation mode selection bit 0 = Two 8-bit timers mode (Timer C/D) 1 = One 16-bit timer mode (Timer 0) Not used
Timer C interrupt pending bit: 0 = No interrupt pending 0 = Clear pending bit (when write) 1 = Interrupt is pending Timer C interrupt enable bit: 0 = Disable interrupt 1 = Enable interrupt
Timer C clock selection bits: 00 = fxx/1024 01 = fxx/512 10 = fxx/8 11 = fxx
Timer C counter enable bit: 0 = Disable counting operation 1 = Enable counting operation Timer C counter clear bit: 0 = No affect 1 = Clear the timer C counter (when write)
Figure 13-1. Timer 0 Control Register (TCCON)
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TIMER 0
BLOCK DIAGRAM
TCCON.5-.4 LSB fXX/1024 fXX/512 fXX/8 / fXX 1 M U X LSB TDDATA Comparator MSB TCDATA TDCNT MSB TCCNT
TCCON.2
TCCON.3 Match
TCINT
TCCON.1 NOTE: When TCCON.7 is '1', one 16-bit Timer 0.
Figure 13-2. Timer 0 Functional Block Diagram
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TIMER 0
S3C9498/F9498
TWO 8-BIT TIMERS MODE (TIMER C and D)
OVERVIEW The 8-bit Timer C and D are the 8-bit general-purpose timers. Timer C have the interval timer mode, and the Timer D have the interval timer mode and PWM mode by using the appropriate TCCON and TDCON setting, respectively. Timer C and D have the following functional components: -- Clock frequency divider with multiplexer - fxx divided by 1024, 512, 8 and 1 for Timer C - fxx divided by 8, 4, 2, or 1 for Timer D -- 8-bit counter (TCCNT, TDCNT), 8-bit comparator, and 8-bit reference data register (TCDATA, TDDATA)) -- Timer C match interrupt generation -- Timer C control register, TCCON (D0H, read/write) -- Timer D have I/O pin for match and PWM output (P1.6, TDOUT) -- Timer D overflow interrupt generation -- Timer D match interrupt generation -- Timer D control register, TDCON (D1H, read/write) Timer C and D Control Register (TCCON, TDCON) You can use the Timer C and D control register, TCCON and TDCON to -- Enable the Timer C (interval timer mode) and D operating (interval timer mode and PWM mode) -- Select the Timer C and D input clock frequency -- Clear the Timer C and D counter, TCCNT and TDCNT -- Enable the Timer C and D interrupt -- Clear Timer C and D interrupt pending conditions
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TIMER 0
TCCON and TDCON are located in address D0H and D1H, and is read/write addressable using register addressing mode. A reset clears TCCON to "00H". This sets Timer C to disable interval timer mode, selects an input clock frequency of fxx/1024, and disables Timer C interrupt. You can clear the Timer C counter at any time during normal operation by writing a "1" to TCCON.3. A reset clears TDCON to "00H". This sets Timer D to enable interval timer mode and disable PWM mode, selects an input clock frequency of fxx/8, and disables Timer C interrupt. You can clear the Timer D counter at any time during normal operation by writing a "1" to TDCON.3. To enable the Timer C interrupt (TCINT) and Timer D interrupt (TDINT) you must write TCCON.7 to "0", TCCON.2 (TDCON.2) and TCCON.1 (TDCON.1) to "1". To generate the exact time interval, you should write TCCON.3 (TDCON.3) and TCCON.0 (TINTPND.4), which cleared counter and interrupt pending bit. To detect an interrupt pending condition when TCINT and TDINT is disabled, the application program polls pending bit, TCCON.0 and TINTPND.4. When a "1" is detected, a Timer C interrupt (TCINT) and Timer D interrupt (TDINT) is pending. When the TCINT and TDINT sub-routine has been serviced, the pending condition must be cleared by software by writing a "0" to the Timer C and D interrupt pending bit, TCCON.0 and TINTPND.4. Also, to enable Timer D overflow interrupt (TDOVF), you must write TCCON.7 to "0", TDCON.2 and TDCON.0 to "1". To generate the exact time interval, you should write TDCON.3 and TINTPND.5, witch cleared counter and interrupt pending bit.
Timer C Control Register (TCCON) E0H, Reset = 00H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
One 16-bit timer or Two 8-bit timers mode: 0 = Two 8-bit timers mode (Timer C/D) 1 = One 16-bit timer mode (Timer 0) Not used
Timer C interrupt pending bit: 0 = No interrupt pending 0 = Clear pending bit (when write) 1 = Interrupt is pending Timer C interrupt enable bit: 0 = Disable interrupt 1 = Enable interrupt
Timer C clock selection bits: 00 = fxx/1024 01 = fxx/512 10 = fxx/8 11 = fxx
Timer C counter enable bit: 0 = Disable counting operation 1 = Enable counting operation
Timer C counter clear bit: 0 = No affect 1 = Clear the timer C counter (when write)
Figure 13-3. Timer C Control Register (TCCON)
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TIMER 0
S3C9498/F9498
Timer B Control Register (TDCON) D1H, Reset = 00H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Timer D operating mode selection bits: 00 = Interval mode 01 = 6-bit PWM mode (OVF interrupt can occur) 10 = 7-bit PWM mode (OVF interrupt can occur) 11 = 8-bit PWM mode (OVF interrupt can occur)
Timer D overflow interrupt enable bit: 0 = Disable overflow interrupt 1 = Enable overflow interrupt Timer D match interrupt enable bit: 0 = Disable match interrupt 1 = Enable match interrupt Timer D count enable bit: 0 = Disable counting operating 1 = Enable counting operating
Timer D clock selection bits: 00 = f xx/8 01 = fx x/4 10 = fx x/2 11 = fxx
Timer D counter clear bit: 0 = No effect 1 = Clear the timer D counter (when write)
Figure 13-4. Timer D Control Register (TDCON)
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TIMER 0
FUNCTION DESCRIPTION Interval Timer Function (Timer C and Timer D) The Timer C and D module can generate an interrupt: the Timer C match interrupt (TCINT) and the Timer D match interrupt (TDINT). The Timer C match interrupt pending condition (TCCON.0) and the Timer D match interrupt pending condition (TINTPND.4) must be cleared by software in the application's interrupt service by means of writing a "0" to the TCCON.0 and TINTPND.4 interrupt pending bit. Even though TCINT and TDINT are disabled, the application's service routine can detect a pending condition of TCINT and TDINT by the software and execute it's sub-routine. When this case is used, the TCINT and TDINT pending bit must be cleared by the application sub-routine by writing a "0" to the corresponding pending bit TCCON.0 and TINTPND.6. In interval timer mode, a match signal is generated when the counter value is identical to the values written to the Timer C or Timer D reference data registers, TCDATA or TDDATA. The match signal generates corresponding match interrupt (TCINT, TDINT) and clears the counter. If, for example, you write the value 20H to TCDATA and 0EH to TCCON, the counter will increment until it reaches 20H. At this point, the Timer C interrupt request is generated, the counter value is cleared, and counting resumes and you write the value 10H to TDDATA, "0" to TCCON.6, and 0EH to TDCON, the counter will increment until it reaches 10H. At this point, TB interrupt request is generated, the counter value is cleared and counting resumes.
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TIMER 0
S3C9498/F9498
TCCON.5-.4 Clear fxx/1024 fxx/512 fXX/8 fXX/1 M U X TCDATA Comparator Match TCCNT R
TCCON.2
TCCON.3
TCCON.1 TCINT
TDCON.1 TDDATA M U X TDCNT R Clear TDCON.5-.4 TDCON.3 TDCON.7-.6 Comparator Match M U X
fXX/8 fXX/4 fXX/2 fXX/1
TDOUT P1.6
NOTE:
When TCCON.7 is '0', two 8-bit timer C/D (Interval mode).
Figure 13-5. Timer C and B Function Block Diagram
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TIMER 0
Pulse Width Modulation Mode (Timer D) Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the TDOUT (P1.6) pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to the Timer D data register. In PWM mode, however, the match signal does not clear the counter. Instead, it runs continuously, overflowing at "FFH", and then continues incrementing from "00H". Although you can use the match signal to generate a Timer D overflow interrupt, interrupts are not typically used in PWM-type applications. Instead, the pulse at the TDOUT pin is held to Low level as long as the reference data value is less than or equal to () the counter value and then the pulse is held to High level for as long as the data value is greater than (>) the counter value. One pulse width is equal to tCLK x 256 (see Figure 13-6).
TDCON.5-.4
6-Bit OVF 7-Bit OVF 8-Bit OVF
MUX
TDCON.6-.7 TINTPND.5
TDOVF
fxx/8 fxx/4 fxx/2 fxx/1 M U X
Up-Counter (Read-Only)
Clear R 6-Bit Match 7-Bit Match 8-Bit Match
TDCON.3 TDCON.0 MUX TDCON.6-.7
8-Bit Comparator
Match
TBOUT(PWM, Interval) P1.6 TDINT (Match INT)
MUX Timer D Buffer Register TDCON.6-.7
TINTPND.6 Pending Bit TDCON.1
Timer D Data Register (Read/Write)
Selected TDOVF TDCON.3
Data Bus
Figure 13- 6. Timer D PWM Function Block Diagram
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NOTES
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UART
14
OVERVIEW
UART
The UART block has a full-duplex serial port with programmable operating modes: There is one synchronous mode and three UART (Universal Asynchronous Receiver/Transmitter) modes: -- Shift Register I/O with baud rate of fxx/(16 x (8bit BRDATA+1)) -- 8-bit UART mode; variable baud rate, fxx/(16 x (8bit BRDATA+1)) -- 9-bit UART mode; fxx/16 -- 9-bit UART mode; variable baud rate, fxx/(16 x (8bit BRDATA+1)) UART receive and transmit buffers are both accessed via the data register, UDATA, is at address FFH. Writing to the UART data register loads the transmit buffer; reading the UART data register accesses a physically separate receive buffer. When accessing a receive data buffer (shift register), reception of the next byte can begin before the previously received byte has been read from the receive register. However, if the first byte has not been read by the time the next byte has been completely received, the first data byte will be lost (Overrun error). In all operating modes, transmission is started when any instruction (usually a write operation) uses the UDATA register as its destination address. In mode 0, serial data reception starts when the receive interrupt pending bit (UARTPND.1) is "0" and the receive enable bit (UARTCON.4) is "1". In mode 1 and 2, reception starts whenever an incoming start bit ("0") is received and the receive enable bit (UARTCON.4) is set to "1". PROGRAMMING PROCEDURE To program the UART modules, follow these basic steps: 1. Configure P0.0 and P0.1 to alternative function (RXD (P0.0), TXD (P0.1)) for UART module by setting the P0CON register to appropriatly value. 2. Load an 8-bit value to the UARTCON control register to properly configure the UART I/O module. 3. For interrupt generation, set the UART interrupt enable bit (UARTCON.1 or UARTCON.0) to "1". 4. When you transmit data to the UART buffer, write transmit data to UDATA, the shift operation starts. 5. When the shift operation (transmit/receive) is completed, UART pending bit (UARTPND.1 or UARTPND.0) is set to "1" and an UART interrupt request is generated.
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UART
S3C9498/F9498
UART CONTROL REGISTER (UARTCON) The control register for the UART is called UARTCON at address FDH. It has the following control functions: -- Operating mode and baud rate selection -- Multiprocessor communication and interrupt control -- Serial receive enable/disable control -- 9th data bit location for transmit and receive operations (mode 2) -- UART transmit and receive interrupt control A reset clears the UARTCON value to "00H". So, if you want to use UART module, you must write appropriate value to UARTCON.
UART Control Register (UARTCON) FDH, R/W, Reset Value: 00H MSB MS1 MS0 MCE RE TB8 RB8 RIE TIE LSB
Operating mode and baud rate selection bits (see table below) Multiprocessor communication(1) enable bit (for modes 2 and 3 only): 0 = Disable 1 = Enable Serial data receive enable bit: 0 = Disable 1 = Enable
Transmit interrupt enable bit: 0 = Disable 1 = Enable Received interrupt enable bit: 0 = Disable 1 = Enable Location of the 9th data bit that was received in UART mode 2 or 3 ("0" or "1")
Location of the 9th data bit to be transmitted in UART mode 2 or 3 ("0" or "1") MS1 MS0 Mode Description(2) Baud Rate 0 0 1 1 NOTES: 1. In mode 2 or 3, if the UARTCON.5 bit is set to "1" then the receive interrupt will not be activated if the received 9th data bit is "0". In mode 1, if UARTCON.5 = "1" then the receive interrut will not be activated if a valid stop bit was not received. In mode 0, the UARTCON.5 bit should be "0" 0 1 0 1 0 1 2 3 Shift register fxx/(16 x (BRDATA +1)) 8-bit UART fxx/(16 x (BRDATA +1)) 9-bit UART fxx/16 9-bit UART fxx/(16 x (BRDATA +1))
2. The descriptions for 8-bit and 9-bit UART mode do not include start and stop bits for serial data receive and transmit.
Figure 14-1. UART Control Register (UARTCON)
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UART
UART INTERRUPT PENDING REGISTER (UARTPND) The UART interrupt pending register, UARTPND is located at address FEH. It contains the UART data transmit interrupt pending bit (UARTPND.0) and the receive interrupt pending bit (UARTPND.1). In mode 0 of the UART module, the receive interrupt pending flag UARTPND.1 is set to "1" when the 8th receive data bit has been shifted. In mode 1 or 2, the UARTPND.1 bit is set to "1" at the halfway point of the stop bit's shift time. When the CPU has acknowledged the receive interrupt pending condition, the UARTPND.1 flag must be cleared by software in the interrupt service routine. In mode 0 of the UART module, the transmit interrupt pending flag UARTPND.0 is set to "1" when the 8th transmit data bit has been shifted. In mode 1 or 2, the UARTPND.0 bit is set at the start of the stop bit. When the CPU has acknowledged the transmit interrupt pending condition, the UARTPND.0 flag must be cleared by software in the interrupt service routine.
UART Pending Register (UARTPND) FEH, R/W, Reset Value: 00H MSB .7 .6 .5 .4 .3 .2 RIP TIP LSB
Not used
UART transmit interrupt pending flag: 0 = Not pending 0 = Clear pending bit (when write) 1 = Interrupt pending UART receive interrupt pending flag: 0 = Not pending 0 = Clear pending bit (when write) 1 = Interrupt pending
NOTES: 1. 2. In order to clear a data transmit or receive interrupt pending flag, you must write a "0" to the appropriate pending bit. To avoid errors, we recommend using load instruction (except for LDB), when manipulating UARTPND values.
Figure 14-2. UART Interrupt Pending Register (UARTPND)
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UART
S3C9498/F9498
UART DATA REGISTER (UDATA)
UART Data Register (UDATA) FFH, R/W, Reset Value: FFH MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Transmit or Receive data
Figure 14-3. UART Data Register (UDATA)
UART BAUD RATE DATA REGISTER (BRDATA) The value stored in the UART baud rate register, (BRDATA), lets you determine the UART clock rate (baud rate).
UART Baud Rate Data Register (BRDATA) D6H, R/W, Reset Value: FFH
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Brud rate data
Figure 14-4. UART Baud Rate Data Register (BRDATA)
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UART
BAUD RATE CALCULATIONS The baud rate is determined by the baud rate data register, 8bit BRDATA Mode 0 Mode 1 Mode 2 Mode 3 baud rate baud rate baud rate baud rate = fxx/(16 x (8Bit BRDATA + 1)) = fxx/(16 x (8Bit BRDATA + 1)) = fxx/16 = fxx/(16 x (8Bit BRDATA + 1))
Table 14-1. Commonly Used Baud Rates Generated by 8-bit BRDATA Mode Mode 2 Mode 0 Mode 1 Mode 3 Baud Rate 0.5 MHz 62,500 Hz 9,615 Hz 38,461 Hz 12,500 Hz 19,230 Hz 9,615 Hz Oscillation Clock 8 MHz 10 MHz 10 MHz 8 MHz 8 MHz 4 MHz 4 MHz BRDATA Decimal x 09 64 12 39 12 25 Hex x 09H 40H 0CH 27H 0CH 19H
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UART
S3C9498/F9498
BLOCK DIAGRAM
SAM86 Internal Data Bus TB8 MS0 MS1 8 BIT BRDATA fxx S D Q CLK Zero Detector UDATA CLK MS0 MS1 RxD (P0.0)
Baud Rate Generator
Write to UDATA
Start Tx Control Tx Clock TIP
Shift EN Send
TxD (P0.1)
TxD (P0.1) Interrupt TIE RIE Shift Clock
RE RIE 1-to-0 Transition Detector
Rx Clock Start
RIP
Receive
Rx Control Shift Shift Value
Bit Detector
MS0 MS1
Shift Register
UDATA RxD (P0.0) SAM86 Internal Data Bus
Figure 14-5. UART Functional Block Diagram
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UART
UART MODE 0 FUNCTION DESCRIPTION In mode 0, UART is input and output through the RxD (P0.0) pin and TxD (P0.1) pin outputs the shift clock. Data is transmitted or received in 8-bit units only. The LSB of the 8-bit value is transmitted (or received) first. Mode 0 Transmit Procedure 1. Select mode 0 by setting UARTCON.6 and .7 to "00B". 2. Write transmission data to the shift register UDATA (FFH) to start the transmission operation. Mode 0 Receive Procedure 1. Select mode 0 by setting UATCON.6 and .7 to "00B". 2. Clear the receive interrupt pending bit (UARTPND.1) by writing a "0" to UARTPND.1. 3. Set the UART receive enable bit (UARTCON.4) to "1". 4. The shift clock will now be output to the TxD (P0.1) pin and will read the data at the RxD (P0.0) pin. A UART receive interrupt (vector 00H-01H) occurs when UARTCON.1 is set to "1".
Write to Shift Register (UDATA)
Shift
RxD (Data Out)
D0
D1
D2
D3
D4
D5
D6
D7
TxD (Shift Clock)
TIP Write to UARTPND (Clear RIP and set RE)
RIP
RE Receive D0 D1 D2 D3 D4 D5 D6 D7 1 2 3 4 5 6 7 8
Shift
RxD (Data In)
TxD (Shift Clock)
Figure 14-6. Timing Diagram for UART Mode 0 Operation
Transmit
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UART
S3C9498/F9498
UART MODE 1 FUNCTION DESCRIPTION In mode 1, 10-bits are transmitted (through the TxD (P0.1) pin) or received (through the RxD (P0.0) pin). Each data frame has three components: -- Start bit ("0") -- 8 data bits (LSB first) -- Stop bit ("1") When receiving, the stop bit is written to the RB8 bit in the UARTCON register. The baud rate for mode 1 is variable. Mode 1 Transmit Procedure 1. Select the baud rate generated by 8bit BRDATA. 2. Select mode 1 (8-bit UART) by setting UARTCON bits 7 and 6 to '01B'. 3. Write transmission data to the shift register UDATA (FFH). The start and stop bits are generated automatically by hardware. Mode 1 Receive Procedure 1. Select the baud rate to be generated by 8bit BRDATA. 2. Select mode 1 and set the RE (Receive Enable) bit in the UARTCON register to "1". 3. The start bit low ("0") condition at the RxD (P0.0) pin will cause the UART module to start the serial data receive operation.
Tx Clock Write to Shift Register (UDATA) Shift TxD TIP Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Stop Bit
Rx Clock RxD D0 D1 D2 D3 D4 D5 D6 D7 Stop Bit
Start Bit
Bit Detect Sample Time Shift RIP Receive
Figure 14-7. Timing Diagram for UART Mode 1 Operation
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UART
UART MODE 2 FUNCTION DESCRIPTION In mode 2, 10-bits are transmitted through the TxD pin or received through the RxD pin. Each data frame has three components: -- Start bit ("0") -- 8 data bits (LSB first) -- Programmable 9th data bit -- Stop bit ("1") The 9th data bit to be transmitted can be assigned a value of "0" or "1" by writing the TB8 bit (UARTCON0.3). When receiving, the 9th data bit that is received is written to the RB8 bit (UARTCON0.2), while the stop bit is ignored. The baud rate for mode 2 is fosc/16 clock frequency. Mode 2 Transmit Procedure 1. Select mode 2 (9-bit UART0) by setting UARTCON bits 6 and 7 to '10B'. Also, select the 9th data bit to be transmitted by writing TB8 to "0" or "1". 2. Write transmission data to the shift register, UDATA (FFH), to start the transmit operation. Mode 2 Receive Procedure 1. Select mode 2 and set the receive enable bit (RE) in the UARTCON register to "1". 2. The receive operation starts when the signal at the RxD pin goes to low level.
Tx Clock Write to Shift Register (UDATA) Shift TxD TIP Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Stop Bit
Rx Clock RxD D0 D1 D2 D3 D4 D5 D6 D7 Stop Bit
Start Bit
Bit Detect Sample Time Shift RIP Receive
Figure 14-8. Timing Diagram for UART Mode 2 Operation
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UART
S3C9498/F9498
UART Mode 3 Function Description In mode 3, 11-bits are transmitted (through the TxD) or received (through the RxD). Mode 3 is identical to mode 2 except for baud rate, which is variable. Each data frame has four components: -- Start bit ("0") -- 8 data bits (LSB first) -- Programmable 9th data bit -- Stop bit ("1") Mode 3 Transmit Procedure 1. Select the baud rate generated by setting BRDATA. 2. Select mode 3 (9-bit UART) by setting UARTCON bits 6 and 7 to '11B'. Also, select the 9th data bit to be transmitted by writing TB8 to "0" or "1" 3. Write transmission data to the shift register, UDATA (FFH), to start the transmit operation. Mode 3 Receive Procedure 1. Select the baud rate to be generated by setting BRDATA. 2. Select mode 3 and set the receive enable bit (RE) in the UARTCON register to "1". 3. The receive operation starts when the signal at the RxD pin goes to low level.
Tx Clock Write to Shift Register (UARTDATA) Shift TxD TIP Start Bit D0 D1 D2 D3 D4 D5 D6 D7 TB8 or Parity bit Stop Bit
RB8 or Parity bit Rx Clock RxD D0 D1 D2 D3 D4 D5 D6 D7 Stop Bit
Start Bit
Bit Detect Sample Time Shift RIP Receive
Figure 14-9. Timing Diagram for UART Mode 3 Operation
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S3C9498/F9498
UART
SERIAL COMMUNICATION FOR MULTIPROCESSOR CONFIGURATIONS The S3C9-series multiprocessor communication features let a "master" S3C9498/F9498 send a multiple-frame serial message to a "slave" device in a multi- S3C9498/F9498 configuration. It does this without interrupting other slave devices that may be on the same serial line. This feature can be used only in UART mode 2 or 3 with the parity disable mode. In mode 2 and 3, 9 data bits are received. The 9th bit value is written to RB8 (UARTCON.2). The data receive operation is concluded with a stop bit. You can program this function so that when the stop bit is received, the serial interrupt will be generated only if RB8 = "1". To enable this feature, you set the MCE bit in the UARTCON registers. When the MCE bit is "1", serial data frames that are received with the 9th bit = "0" do not generate an interrupt. In this case, the 9th bit simply separates the address from the serial data. Sample Protocol for Master/Slave Interaction When the master device wants to transmit a block of data to one of several slaves on a serial line, it first sends out an address byte to identify the target slave. Note that in this case, an address byte differs from a data byte: In an address byte, the 9th bit is "1" and in a data byte, it is "0". The address byte interrupts all slaves so that each slave can examine the received byte and see if it is being addressed. The addressed slave then clears its MCE bit and prepares to receive incoming data bytes. The MCE bits of slaves that were not addressed remain set, and they continue operating normally while ignoring the incoming data bytes. While the MCE bit setting has no effect in mode 0, it can be used in mode 1 to check the validity of the stop bit. For mode 1 reception, if MCE is "1", the receive interrupt will be issue unless a valid stop bit is received.
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UART
S3C9498/F9498
Setup Procedure for Multiprocessor Communications Follow these steps to configure multiprocessor communications: 1. Set all S3C9498/F9498 devices (masters and slaves) to UART mode 2 or 3 2. Write the MCE bit of all the slave devices to "1". 3. The master device's transmission protocol is: -- First byte: the address identifying the target slave device (9th bit = "1") -- Next bytes: data (9th bit = "0") 4. When the target slave receives the first byte, all of the slaves are interrupted because the 9th data bit is "1". The targeted slave compares the address byte to its own address and then clears its MCE bit in order to receive incoming data. The other slaves continue operating normally.
Full-Duplex Multi-S3C9498/F9498 Interconnect
TxD
RxD Master
TxD
RxD
TxD
RxD
TxD
RxD
Slave 1 S3C9498/ F9498
Slave 2 S3C9498/ F9498
...
Slave n S3C9498/ F9498
S3C9498/ F9498
Figure 14-10. Connection Example for Multiprocessor Serial Data Communications
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SERIAL I/O INTERFACE
15
OVERVIEW
SERIAL I/O INTERFACE
Serial I/O module, SIO can interface with various types of external devices that require serial data transfer. The components of each SIO function block are: -- 8-bit control register (SIOCON) -- Clock selection logic -- 8-bit data buffer (SIODATA) -- 8-bit presale (SIOPS) -- 3-bit serial clock counter -- Serial data I/O pins (SI, SO) -- External clock input pin (SCK) SIO module can transmit or receive 8-bit serial data at a frequency determined by its corresponding control register settings. To ensure flexible data transmission rates, you can select an internal or external clock source. PROGRAMMING PROCEDURE To program the SIO module, follow these basic steps: 1. Configure the I/O pins at port 3 (SO, SCK, SI) by loading the appropriate value to the P3CON Register. 2. Load an 8-bit value to the SIOCON control register to properly configure the serial I/O module. In this operation, SIOCON.2 must be set to "1" to enable the data shifter. 3. For interrupt generation, set the serial I/O interrupt enable bit (SIOCON.1) to "1". 4. When you the transmit data to the serial buffer, write data to SIODATA and set SIOCON.3 to 1, the shift operation starts. 5. When the shift operation (transmit/receive) is completed, the SIO pending bit (SIOCON.0) is set to "1" and an SIO interrupt request is generated.
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SERIAL I/O INTERFACE
S3C9498/F9498
SERIAL I/O CONTROL REGISTERS (SIOCON) The control registers for serial I/O interface, SIOCON, is located at F1H. It has the control settings for SIO module. -- Clock source selection (internal or external) for shift clock -- Interrupt enable -- Edge selection for shift operation -- Clear 3-bit counter and start shift operation -- Shift operation (transmit) enable -- Mode selection (transmit/receive or receive-only) -- Data direction selection (MSB first or LSB first) A reset clears the SIOCON value to "00H". This configures the corresponding module with an internal clock source at the SCK, selects receive-only operating mode, and clears the 3-bit counter. The data shift operation and the interrupt are disabled. The selected data direction is MSB-first.
SIO Control Registers (SIOCON) F1H, R/W, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
SIO shift clock select bit: 0 = Internal clock (P.S clock) 1 = External clock (SCK) Data direction control bit: 0 = MSB-first mode 1 = LSB-first mode SIO mode selction bit: 0 = Rececive-only mode 1 = Transmit/receive mode Shift clock edge selction bit: 0 = Tx falling edges, Rx at rising edges 1 = Tx rising edges, Rx at falling edges
SIO Interrupt pending bit: 0 = No interrupt pending 0 = Clear pending condition (when write) 1 = Interrupt is pending SIOinterrupt enable bit: 0 = Disable SIO interrupt 1 = Enable SIO interrupt SIO shift operation enable bit: 0 = Disable shifter and clock counter 1 = Enable shfter and clock counter
SIO counter clear and shift start bit: 0 = No action 1 = Clear 3-bit counter and start shifting
Figure 15-1. Serial I/O Interface Control Register (SIOCON)
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S3C9498/F9498
SERIAL I/O INTERFACE
SIO PRESCALER REGISTER (SIOPS) The control register for serial I/O interface module, SIOPS is located at F4H. The value stored in the SIO prescaler registers, SIOPS, lets you determine the SIO clock rate (baud rate) as follows: Baud rate = Input clock(Xin/4) / (SIOP+ 1), or external SCK input clock
SIO Pre-Scaler Registers (SIOPS) F4H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Baud rate = (XIN/4)/(SIOPS + 1)
Figure 15-2. SIO Pre-Scaler Register (SIOPS)
CLK
3-Bit Counter Clear SIOCON.3
SIOCON.0 Pending
SIO INT
SIOCON.7 (Shift Clock Source Select)
SIOCON.1 (Interrupt Enable)
SIOCON.4 (Edge Select) SCK SIOPS(F4H) XIN/2 8-Bit Prescaler 1/2 MUX CLK
SIOCON.2 (Shift Enable)
SIOCON.5 (Mode Select) SO SIOCON.6 (LSB/MSB First Mode Select)
8-Bit SIO Shift Buffer (SIODATA)
Toggle Prescaler Value = 1/(SIOPS + 1) SI
8
Data Bus
Figure 15-3. SIO Functional Block Diagram
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SERIAL I/O INTERFACE
S3C9498/F9498
SCK
SI
D17
D16
D15
D14
D13
D12
D11
D10
SO
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
IRQS Set SIOCON.3
Transmit Complete
Figure 15-4. Serial I/O Timing in Transmit-Receive Mode (Tx at falling, SIOCON.4 = 0)
SCK
SI
D17
D16
D15
D14
D13
D12
D11
D10
SO
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
IRQS Set SIOCON.3
Transmit Complete
Figure 15-5. Serial I/O Timing in Transmit-Receive Mode (Tx at rising, SIOCON.4 = 1)
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SERIAL I/O INTERFACE
Shift Clock
Data Input
D7
D6
D5
D4
D3
D2
D1
D0
Data Output
High Impedance
IRQ5
Start
Transmit Complete
Figure 15-6. Serial I/O Timing in Receive-Only Mode
F PROGRAMMING TIP -- SIO
ORG VECTOR ORG INITIAL: LD LD LD LD
* *
0000H 00H, INT_9498 0100H SYM, #00H BTCON, #10100010B CLKCON, #00011000B SP, #0C0H ; ; ; ; Global/Fast interrupt disable -> SYM Watch-dog disable non-divided CPU clock 9498 a 00~BF (After decrease, push data) ; S3C9498/F9498 has only one interrupt vector
LD
* *
P3CON, #10111100B
; SIO setting
LD LD
* *
SIOCON, #00100110B SIOPS, #20
; Enable SIO/Interrupt ; setting baud rate
EI
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SERIAL I/O INTERFACE
S3C9498/F9498
F PROGRAMMING TIP -- SIO (Continued)
MAIN:
* * *
CALL
* * *
SUB_SIO
; Data transmit routine
JP SUB_SIO: LD OR
* *
MAIN SIODATA, TRANSBUF SIOCON, #00001000B ; 1-byte transmission ; Shift start (8-bit transmit)
RET INT_9498: LD AND CP JP INT_SIO: AND
* * *
; S3C9498/F9498 has just one interrupt vector R0, SIOCON R0, #00000011B R0, #00000011B EQ, INT_SIO SIOCON, #11111110
; SIOCON's pending bit & INT. enable bit check ; Pending bit clear
IRET
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S3C9498/F9498
12-BIT PWM
16
OVERVIEW
12-BIT PWM (PULSE WIDTH MODULATION)
This microcontroller has the 12-bit PWM circuit. The operation of all PWM circuit is controlled by a single control register, PWMCON. The PWM counter is a 12-bit incrementing counter. It is used by the 12-bit PWM circuits. To start the counter and enable the PWM circuits, you set PWMCON.2 to "1". If the counter is stopped, it retains its current count value; when re-started, it resumes counting from the retained count value. When there is a need to clear the counter you set PWMCON.3 to "1". You can select a clock for the PWM counter by set PWMCON.6-.7. Clocks which you can select are Fosc/256, Fosc/64, Fosc/8, Fosc/1.
FUNCTION DESCRIPTION
PWM The 12-bit PWM circuits have the following components: -- 6-bit comparator and extension cycle circuit -- 6-bit reference data registers (PWMDATA) -- 6-bit extension data registers (PWMEX) -- PWM output pins (P2.7/PWM) PWM counter The PWM counter is a 12-bit incrementing counter comprised of a lower 6-bit counter and an upper 6-bit counter. To determine the PWM module's base operating frequency, the lower byte counter is compared to the PWM data register value. In order to achieve higher resolutions, the six bits of the upper counter can be used to modulate the "stretch" cycle. To control the "stretching" of the PWM output duty cycle at specific intervals, the 6-bit extended counter value is compared with the 6-bit value (bits 7-2) that you write to the module's extension register.
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12-BIT PWM
S3C9498/F9498
PWM data and extension registers PWM (duty) data registers, located in E4H , determine the output value generated by each 12-bit PWM circuit. These registers, PWM is read/write addressable. -- 8-bit data register PWMDATA, of which only bits 5-0 are used. -- 8-bit extension registers PWMEX (E5H), of which only bits 7-2 are used To program the required PWM output, you load the appropriate initialization values into the 6-bit data registers (PWMDATA) and the 6-bit extension registers (PWMEX). To start the PWM counter, or to resume counting, you set PWMCON.2 to "1". A reset operation disables all PWM output. The current counter value is retained when the counter stops. When the counter starts, counting resumes at the retained value. PWM clock rate The timing characteristics of both 12-bit output channels are identical, and are based on the Fosc clock frequency. The counter clock value is determined by the setting of PWMCON.6-.7. Table 16-1. PWM Control and Data Registers Register Name PWM data registers PWM control registers Mnemonic PWMDATA PWMEX PWMCON Address E4H E5H EDH Function 6-bit PWM basic cycle frame value 6-bit extension ("stretch") value PWM counter stop/start (resume), and Fosc clock settings
PWM function Description The PWM output signal toggles to Low level whenever the lower 6-bit counter matches the reference value stored in the module's data register (PWMDATA). If the value in the PWMDATA register is not zero, an overflow of the lower counter causes the PWM output to toggle to High level. In this way, the reference value written to the data register determines the module's base duty cycle. The value in the 6-bit extension counter is compared with the extension settings in the 6-bit extension data register (PWMEX). This 6-bit extension counter value, together with extension logic and the PWM module's extension register , is then used to "stretch" the duty cycle of the PWM output. The "stretch" value is one extra clock period at specific intervals, or cycles (see Table 16-2). If, for example, the value in the extension register is '04H', the 32nd cycle will be one pulse longer than the other 63 cycles. If the base duty cycle is 50 %, the duty of the 32nd cycle will therefore be "stretched" to approximately 51% duty. For example, if you write 80H to the extension register, all odd-numbered pulses will be one cycle longer. If you write FCH to the extension register, all pulses will be stretched by one cycle except the 64th pulse. PWM output goes to an output buffer and then to the corresponding PWM output pin. In this way, you can obtain high output resolution at high frequencies.
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12-BIT PWM
Table 16-2. PWM output "stretch" Values for Extension Registers PWMEX PWMEX Bit 7 6 5 4 3 2 1 0 "Stretched" Cycle Number 1, 3, 5, 7, 9, . . . , 55, 57, 59, 61, 63 2, 6, 10, 14, . . . , 50, 54, 58, 62 4, 12, 20, . . . , 44, 52, 60 8, 24, 40, 56 16, 48 32 Not used Not used
0H PWM Clock: 4MHz 0H PWMDATA Register Values: 1H 250ns
40H
80H
250ns
20H
8ms
8ms
3FH
250ns
Figure 16-1. 12-Bit PWM Basic Waveform
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12-BIT PWM
S3C9498/F9498
0H PWM Clock: PWMDATA Register Values: 02H 4MHz
40H
2H
500ns
PWMEX Register Values: (Extended Value is 04H)
1st 4H 32th
64th 1st
32th
64th
0H 4MHz
40H
750ns
Figure 16-2. 12-Bit Extended PWM Waveform
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12-BIT PWM
PWM CONTROL REGISTER (PWMCON) The control register for the PWM module, PWMCON, is located at register address EDH. PWMCON is used the 12-bit PWM modules. Bit settings in the PWMCON register control the following functions: -- PWM counter clock selection -- PWM data reload interval selection -- PWM counter clear -- PWM counter stop/start (or resume) operation -- PWM counter overflow (upper 6-bit counter overflow) interrupt control A reset clears all PWMCON bits to logic zero, disabling the entire PWM module.
PWM Control Registers (PWMCON) EDH, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
PWM input clock selection bits: 00 = fosc/256 01 = fosc/64 10 = fosc/8 11 = fosc/1 PWM data reload interval selection bit: 0 = Reload from 12-bit up counter overflow 1 = Reload from 6-bit up counter overflow Not used
PWM 12-bit OVF Interrupt pending bit: 0 = No interrupt pending 0 = Clear pending condition (when write) 1 = Interrupt is pending PWM Overflow Interrupt Enable bit (12-bit Counter Overflow) 0 = Disable PWM OVF interrupt 1 = Enable PWM OVF interrupt PWM counter enable bit: 0 = Stop counter 1 = Start (resume countering)
PWM counter clear bit: 0 = No effect 1 = Clear the 12-bit up counter
Figure 16-3. PWM/Capture Module Control Register (PWMCON)
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12-BIT PWM
S3C9498/F9498
6-Bit Basic Register PWMDATA Reload (overflow of the lower 6-bit counter) 6 6-Bit Buffer
fosc/256 fosc/64 fosc/8 fosc/1 6 MUX PWMCON.6-7 Lower 6-Bit Counter Upper 6-Bit Counter Pending PWMCON.0 PWMCON.1 PWMCON.2 Extension Control Logic OVFINT 6 6-Bit Comparator "1" When PWMDATA > Counter "0" When PWMDATA = Counter < PWMDATA = Counter P2.7/PWM
(1,3,...,61,63) Bit 7 6-Bit Extension Registers (PWMEX)
32 Bit 2
Figure 16-4. PWM/Capture Module Functional Block Diagram
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12-BIT PWM
F PROGRAMMING TIP -- Programming the PWM Module to Sample Specifications
ORG VECTOR ORG INITIAL: LD LD LD LD
* *
0000H 00H, INT_9498 0100H SYM, #00H BTCON, #10100010B CLKCON, #00011000B SP, #0C0H ; ; ; ; Global/Fast interrupt disable -> SYM Watch-dog disable non-divided CPU clock 9498 00-BF (After decrease, push data) ; S3C9498/F9498 has only one interrupt vector
LD LD LD LD
* * *
P2CONH, #0C0H PWMEX, #0 PWMDATA, #20H PWMCON, #00000100B
; P0.7 PWM0 output ; ; ; ; Extension register setting Data register setting Start counting Half duty PWM wave out to P0.7
EI MAIN:
* * *
CALL
* * *
SUB_ROUTINE
JP SUB_ROUTINE: NOP
* * *
MAIN
RET
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S3C9498/F9498
NOTES
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S3C9498/F9498
A/D CONVERTER
17
OVERVIEW
10-BIT ANALOG-TO-DIGITAL CONVERTER
The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at one of the nine input channels to equivalent 10-bit digital values. The analog input level must lie between the AVREF and VSS values. The A/D converter has the following components: -- Analog comparator with successive approximation logic -- D/A converter logic (resistor string type) -- ADC control register (ADCON) -- Eight multiplexed analog data input pins (AD0 - AD7), alternately digital data I/O port -- 10-bit A/D conversion data output register (ADDATAH/L) -- AVREF, AVSS (AVSS is internally connected to VSS )
FUNCTION DESCRIPTION
To initiate an analog-to-digital conversion procedure, at the first you must set port control register(P1CONH/L) for AD analog input. And you write the channel selection data in the A/D converter control register ADCON.4-.7 to select one of the eight analog input pins (AD0-7) and set the conversion start bit, ADCON.0. The read-write ADCON register is located at address FCH. The unused pin can be used for normal I/O. During a normal conversion, ADC logic initially sets the successive approximation register to 200H (the approximate half-way point of a 10-bit register). This register is then updated automatically during each conversion step. The successive approximation block performs 10-bit conversions for one input channel at a time. You can dynamically select different channels by manipulating the channel selection bit value (ADCON.4 - 7) in the ADCON register. To start the A/D conversion, you should set the enable bit, ADCON.0. When a conversion is completed, the end-of-conversion (EOC) bit is automatically set to 1 and the result is dumped into the ADDATAH/L register where it can be read. The A/D converter then enters an idle state. Remember to read the contents of ADDATAH/L before another conversion starts. Otherwise, the previous result will be overwritten by the next conversion result. NOTE Because the A/D converter has no sample-and-hold circuitry, it is very important that fluctuation in the analog level at the AD0-AD7input pins during a conversion procedure be kept to an absolute minimum. Any change in the input level, perhaps due to noise, will invalidate the result. If the chip enters to STOP or IDLE mode in conversion process, there will be a leakage current path in A/D block. You must use STOP or IDLE mode after ADC operation is finished.
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A/D CONVERTER
S3C9498/F9498
CONVERSION TIMING The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set-up A/D conversion. Therefore, total of 50 clocks are required to complete a 10-bit conversion: When Fxx/8 is selected for conversion clock with a 8 MHz fxx clock frequency, one clock cycle is 1 us. Each bit conversion requires 4 clocks, the conversion rate is calculated as follows: 4 clocks/bit x 10 bits + set-up time = 50 clocks, 50 clock x 1us = 50 us at 8 MHz A/D CONVERTER CONTROL REGISTER (ADCON) The A/D converter control register, ADCON, is located at address FCH. It has three functions: -- Analog input pin selection (bits 4, 5, 6, and 7) -- A/D conversion End-of-conversion (ECO) status (bit 3) -- A/D conversion speed selection (bits 1,2) -- A/D operation start (bit 0) After a reset, the start bit is turned off. You can select only one analog input channel at a time. Other analog input pins (ADC0-ADC7)can be selected dynamically by manipulating the ADCON.4-7 bits. And the pins not used for analog input can be used for normal I/O function.
A/D Converter Control Register (ADCON) FCH, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
End-of-conversion (ECO) A/D input pin selection bits: A/D conversion Start bit: status bit: 0000 = ADC0 0 = Disable operation 0 = A/D conversion 0001 = ADC1 1 = Start operation (Auto-clear) is in progress 0010 = ADC2 1 = A/D conversion 0011 = ADC3 complete 0100 = ADC4 0101 = ADC5 Clock source selection bits: 0110 = ADC6 00 = fxx/16 (fosc = 8MHz) 0111 = ADC7 01 = fxx/8 (fosc = 8MHz) other values = Connected with GND internally 10 = fxx/4 (fosc = 8MHz) 11 = fxx (fosc = 2.5MHz)
NOTE:
Maximum ADC clock input = 4MHz
Figure 17-1. A/D Converter Control Register (ADCON)
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A/D CONVERTER
Conversion Data Register High Byte (ADDATAH) FAH, Ready only MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Conversion Data Register Low Byte (ADDATAL) FBH, Ready only MSB x x x x x x .1 .0 LSB
Figure 17-2. A/D Converter Data Register (ADDATAH/L)
INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block, the analog input voltage level is compared to the reference voltage. The analog input level must remain within the range VSS to AVREF (usually, AVREF = VDD). Different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step. The reference voltage level for the first conversion bit is always 1/2 AVREF.
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A/D CONVERTER
S3C9498/F9498
BLOCK DIAGRAM
- A/D Converter Control Register ADCON (FCH) ADCON.7-.4 ADCON.0 (ADC Start) Control Circuit M U L T I P L E X E R Clock Selector ADCON.2-.1 + Analog Comparator Successive Approximation Circuit ADCON.3 (EOC Flag)
ADC0/P1.0 ADC1/P1.1 ADC2/P1.2
ADC6/P0.6 ADC7/P0.7
AVref D/A Converter VSS
Conversion Result ADDATAH (FAH) ADDATAL (FBH)
To data bus
Figure 17-3. A/D Converter Functional Block Diagram
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A/D CONVERTER
INTERNAL A/D CONVERSION PROCEDURE 1. Analog input must remain between the voltage range of VSS and AVREF. 2. 3. Configure P1.0-P1.7 for analog input before A/D conversions. To do this, you load the appropriate value to the P1CONH and P1CONL (for ADC0-ADC7) registers. Before the conversion operation starts, you must first select one of the eight input pins (ADC0-ADC7) by writing the appropriate value to the ADCON register.
4. When conversion has been completed, (50 clocks have elapsed), the EOC, ADCON.3 flag is set to "1", so that a check can be made to verify that the conversion was successful. 5. The converted digital value is loaded to the output register, ADDATAH (8-bit) and ADDATAL (2-bit), then the ADC module enters an idle state. 6. The digital conversion result can now be read from the ADDATAH and ADDATAL register.
VDD Reference Voltage Input VDD
104
R AVref
Analog Input Pin 101
ADC0-ADC7
S3F9498
Vss
NOTE:
The symbol "R" signifies an offset resistor with a value of from 50 to. 100
Figure 17-4. Recommended A/D Converter Circuit for Highest Absolute Accuracy
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A/D CONVERTER
S3C9498/F9498
NOTES
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S3C9498/F9498
ELECTRICAL DATA
18
OVERVIEW
ELECTRICAL DATA
In this section, the following S3C9498/F9498 electrical characteristics are presented in tables and graphs: -- Absolute maximum ratings -- D.C. electrical characteristics -- A.C. electrical characteristics -- Operating Voltage Range -- Schmitt trigger input characteristics -- Oscillator characteristics -- Oscillation stabilization time -- Data retention supply voltage in Stop mode -- Stop mode release timing when initiated by a RESET -- Power-on RESET circuit characteristics -- A/D converter electrical characteristics
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ELECTRICAL DATA
S3C9498/F9498
Table 1 8-1. Absolute Maximum Ratings (TA = 25 C) Parameter Supply voltage Input voltage Output voltage Output current high Symbol VDD VI VO I OH All input ports All output ports One I/O pin active All I/O pins active Output current low I OL One I/O pin active Total pin current for ports 1, 2, 3 Total pin current for ports 0 Operating temperature Storage temperature TA TSTG - - Conditions - Rating - 0.3 to + 6.5 - 0.3 to V DD + 0.3 - 0.3 to VDD + 0.3 - 25 - 80 + 30 + 100 + 200 - 25 to + 85 - 65 to + 150 C C mA Unit V V V mA
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ELECTRICAL DATA
Table 18-2. D.C. Electrical Characteristics (TA = - 25 C to + 85 C, V DD = 2.2 V to 5.5 V)
Parameter Input high voltage Symbol VIH1 VIH3 Input low voltage VIL1 VIL2 Output high voltage Output low voltage VOH VOL ILIH1 ILIH2 Input low leakage current ILIL1 ILIL2 Output high leakage current Output low leakage current Pull-up resistor ILOH ILOL RP Conditions Ports 0, 1, 2, 3 and nRESET XIN and XOUT Ports 0, 1, 2, 3 and nRESET XIN and XOUT IOH = - 3 mA ports 0-3 IOL = 8 mA port 0 -3 All input pins except ILIH2 XIN , XOUT All input pins except ILIL2 XIN , XOUT All output pins All output pins VIN = 0 V Port 0-3 VDD= 4.5 to 5.5 V VDD= 4.5 to 5.5 V VIN = VDD VIN = VDD VIN = 0 V VIN = 0 V VOUT = VDD VOUT = 0 V VDD = 5V, TA = 25 C VDD = 4.5 to 5.5 V VDD = 2.2 to 3 V - - - 25 - - 50 - - VDD - 1.0 - VDD - 0.4 0.4 VDD= 2.2 to 5.5 V VDD= 2.2 to 5.5 V Min 0.8 VDD VDD - 0.1 - - 0.2 V DD 0.1 - V V Typ - Max VDD Unit V
2.0
V A
Input high leakage current
-
-
1
20 -1 A
- 20 2 -2 100 A A k
Supply current
IDD1
RUN mode 8-MHz CPU clock 3-MHz CPU clock
-
6 2 1.5 1
12 4 3 2 3
mA
IDD2
Idle mode 8-MHz CPU VDD = 4.5 to 5.5 V clock 3-MHz CPU clock VDD = 2.2 to 3 V VDD = 4.5 to 5.5 V TA = 25 C VDD = 2.2 to 3 V TA = 25 C
IDD3
Stop mode, disable
LVR
-
1
A
0.5
2
NOTE:
D.C. electrical values for Supply current (IDD1 to IDD3) do not include current drawn through internal pull-up resisters, output port drive current, LVR, and ADC.
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ELECTRICAL DATA
S3C9498/F9498
Table 18-3. A.C. Electrical Characteristics (TA = -25 C to + 85 C, VDD = 2.2 V to 5.5 V) Parameter Interrupt input high, low width nRESET input low width Symbol t INTH, t INTL t RSL
-
Conditions Port 1(INT0, INT1) V DD = 5V 10% Input V DD = 5V 10%
Min -
Typ 200
Max -
Unit ns
-
1
-
us
1/tCPU tINTL tRSL tINTH
0.8 VDD 0.2 VDD
NOTE:
The unit tcpu means one CPU clock period.
Figure 18-1. Input Timing Measurement Points
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ELECTRICAL DATA
CPU Clock
8MHz
4MHz 3MHz 2MHz 1MHz
1
2
3
4
4.5 5
5.5
6
7
2.2 2.7 Supply Voltage (V)
Figure 18-2. Operating Voltage Range (S3C9498/F9498)
VOUT VDD
A = 0.2 VDD B = 0.4 VDD C = 0.6 VDD D = 0.8 VDD
VSS
A
B
C
D
VIN
0.3 VDD
0.7 VDD
Figure 18-3. Schimtt Trigger Input Characteristic Diagram
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ELECTRICAL DATA
S3C9498/F9498
Table 18-4. Oscillator Characteristics (TA = - 25 C to + 85 C) Oscillator Main crystal or ceramic Clock Circuit
XIN XOUT
Test Condition VDD = 4.5 to 5.5 V VDD = 3.0 to 4.5 V
Min 1
Typ -
Max 8
Unit MHz
C1
C2
External clock (Main system)
XIN
XOUT
VDD = 4.5 to 5.5 V VDD = 3.0 to 4.5 V
1
-
8
Table 18-5. Oscillation Stabilization Tim e (TA = - 25 C to + 85 C, V DD = 2.2 V to 5.5 V) Oscillator Main crystal Main ceramic External clock (main system) Oscillator stabilization wait time fosc > 1.0 MHz Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range. XIN input high and low width (tXH, t XL) t WAIT when released by a reset (1) t WAIT when released by an interrupt (2) Test Condition Min - - 50 - - Typ - - - 216 /fosc - Max 20 10 - - - ns ms Unit ms
NOTES: 1. fosc is the oscillator frequency. 2. The duration of the oscillator stabilization wait time, tWAIT, when it is released by an interrupt is determined by the setting in the basic timer control register, BTCON.
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ELECTRICAL DATA
Table 18-6. Data Retention Supply Voltage in Stop Mode (TA = - 25 C to + 85 C, V DD = 2.2 V to 5.5V) Parameter Data retention supply voltage Data retention supply current
NOTE:
Symbol V DDDR IDDDR
Conditions Stop mode Stop mode; VDDDR = 2.2 V
Min 2.2 -
Typ - 0.1
Max 5.5 5
Unit V A
Supply current does not include current drawn through internal pull-up resistors or external output current loads.
Internal RESET Operation Stop Mode Data Retention Mode
Oscillation Stabilization Time Normal Operating Mode
~ ~ ~ ~
VDD
Execution Of Stop Instrction RESET
VDDDR
0.8 VDD 0.2 VDD tWAIT
NOTE:
tWAIT is the same as 4096 x 16 x 1/fosc
Figure 18-4. Stop Mode Release Timing When Initiated by a RESET
Table 1 8-7. LVR(Low Voltage Reset) Circuit Characteristics (TA = 25 C) Parameter LVR voltage level Symbol VLVR Test Condition TA = 25 C Min 2.7 Typ 3.0 Max 3.3 Unit V
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ELECTRICAL DATA
S3C9498/F9498
Table 18-8. A/D Converter Electrical Characteristics (TA = - 25 C to + 85 C, VDD = 2.2 V to 5.5 V, VSS = 0 V) Parameter Total accuracy Symbol Test Conditions VDD = 5.12 V CPU clock = 8 MHz AV REF = 5.12 V AV SS = 0 V Integral linearity error Differential linearity error Offset error of top Offset error of bottom Conversion time(1) Analog input voltage Analog input impedance ADC reference voltage ADC reference ground Analog input current ADC block current (2) ILE DLE EOT EOB t CON V IAN RAN AVREF AVSS IADIN IADC fosc = 8 MHz - - - - AV REF = VDD = 5 V AV REF = VDD = 5 V AV REF = VDD = 3 V AV REF = VDD = 5 V Power down mode - " " " " - - - - 25 AVSS 2 2.5 VSS - - - - 1 1 - - - - - - 1 0.5 100 3 1 3 3 - AVREF - VDD V SS + 0.3 10 3 1.5 500 nA A mA s V M V V LSB Min - Typ - Max 3 Unit LSB
NOTES: 1. `Conversion time' is the time required from the moment a conversion operation starts until it ends. 2. IADC is operating current during A/D conversion.
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S3C9498/F9498
ELECTRICAL DATA
Digital Output
Analog Input AVSS VEOB V2 V(K-1) V(K) VEOT AVREF
Figure 18-5. Definition of DLE and ILE
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ELECTRICAL DATA
S3C9498/F9498
NOTES
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S3C9498/F9498
MECHANICAL DATA
19
OVERVIEW
#32
MECHANICAL DATA
The S3C9498/F9498 is available in a 32-pin SDIP package (Samsung: 32-SDIP-400) and a 32-pin SOP package (32-SOP-450A) and 30-pin package(30-SDIP-400) and a 28-pin SOP package (28-SOP-375). Package dimensions are shown in Figures19-1, 19-2, 19-3 and 19-4
#17
12.00 0.3
8.34 0.2
2.00 0.2
2.40 MAX
#1 19.90 0.2
#16
0.20
+ 0.1 - 0.05
(0.43)
0.40 0.1
1.27
NOTE: Dimensions are in millimeters
Figure 19-1. 32-SOP-450A Package Dimensions
0.05 MIN
0.78 0.2
32-SOP-450A
11.43
0-8
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MECHANICAL DATA
S3C9498/F9498
#32
#17
0-15
9.10 ?0.20
#1
#16
27.88 MAX 27.48 ?0.20
0.51 MIN
0.45 ?0.10 (1.37) 1.00 ?0.10 1.778
NOTE:
Dimensions are in millimeters.
Figure 19-2. 32-SDIP-400 Package Dimensions
19-2
3.30 ?0.30
5.08 MAX
3.80 ?0.20
0.2 5
+0 . - 0 10 .05
32-SDIP-400
10.16
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S3C9498/F9498
MECHANICAL DATA
#28
#15
10.45 0.3
7.70 0.2
#1 18.02 MAX 17.62 0.2
#14 2.15 0.1 2.50 MAX 0.15
+ 0.10 - 0.05
(0.56)
0.41 0.1
1.27
NOTE: Dimensions are in millimeters
Figure 19-3. 28-SOP-375 Package Dimensions
0.05 MIN
0.60 0.2
28-SOP-375
9.53
8
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MECHANICAL DATA
S3C9498/F9498
#30
#16
0-15
0.2
8.94
#1
#15
27.88MAX 27.48 0.2
0.51 MIN
0.56 (1.30) 1.12
0.1 0.1
1.778
NOTE:
Dimensions are in millimeters.
Figure 19-4. 30-Pin SDIP Package Dimensions
19-4
3.30 0.3
5.08 MAX
3.81
0.2
0.2 5
+0 - 0 .1 .05
30-SDIP-400
10.16
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S3C9498/F9498
MTP
20
OVERVIEW
MTP
The S3C9498/F9498 single-chip CMOS microcontroller is the MTP (Multi Time Programmable) version of the S3C9498 microcontroller. It has an on-chip Flash ROM instead of masked ROM. The Flash ROM is accessed by serial data format. The S3C9498/F9498 is fully compatible with the S3C9498, in function, in D.C. electrical characteristics, and in pin configuration. Because of its simple programming requirements, the S3F9488 is ideal for use as an evaluation chip for the S3C9498.
VSS XOUT XIN (Vpp)TEST RxD/P0.0 TxD/P0.1 nRESET/P0.2 P3.3 P3.4 AVREF INT0/ADC0/P1.0 INT1/ADC1/P1.1 ADC2/P1.2 ADC3/P1.3 ADC4/P1.4 ADC5/P1.5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
S3C9498/ F9498
(Top View) 32-SOP 32-SDIP
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VDD P3.2/SCK(SCLK) P3.1/SO(SDAT) P3.0/SI P2.7/PWM P2.6/T1CAP P2.5/T1OUT P3.6 P3.5 P2.4/T1CK P2.3/TBOUT P2.2/TACAP P2.1/TACK P2.0/TAOUT P1.7/ADC7 P1.6/ADC6/TDOUT
Figure 20-1. Pin Assignment Diagram (32-Pin Package)
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MTP
S3C9498/F9498
VSS XOUT XIN (Vpp)TEST RxD/P0.0 TxD/P0.1 nRESET/P0.2 P3.3 AVREF INT0/ADC0/P1.0 INT1/ADC1/P1.1 ADC2/P1.2 ADC3/P1.3 ADC4/P1.4 ADC5/P1.5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
S3C9498/ F9498
(Top View) 30-SDIP
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VDD P3.2/SCK(SCLK) P3.1/SO(SDAT) P3.0/SI P2.7/PWM P2.6/T1CAP P2.5/T1OUT P3.5 P2.4/T1CK P2.3/TBOUT P2.2/TACAP P2.1/TACK P2.0/TAOUT P1.7/ADC7 P1.6/ADC6/TDOUT
Figure 20-2. Pin Assignment Diagram (30-Pin Package)
VSS XOUT XIN (Vpp)TEST RxD/P0.0 TxD/P0.1 nRESET/P0.2 AVREF INT0/ADC0/P1.0 INT1/ADC1/P1.1 ADC2/P1.2 ADC3/P1.3 ADC4/P1.4 ADC5/P1.5
1 2 3 4 5 6 7 8 9 10 11 12 13 14
S3C9498/ F9498
(Top View) 28-SOP
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDD P3.2/SCK(SCLK) P3.1/SO(SDAT) P3.0/SI P2.7/PWM P2.6/T1CAP P2.5/T1OUT P2.4/T1CK P2.3/TBOUT P2.2/TACAP P2.1/TACK P2.0/TAOUT P1.7/ADC7 P1.6/ADC6/TDOUT
Figure 20-3. Pin Assignment Diagram (28-Pin Package)
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S3C9498/F9498
MTP
Table 20-1. Descriptions of Pins Used to Read/Write the Flash ROM Main Chip Pin Name P3.1 Pin Name SDAT Pin No. 30 (32-pin) 28 (30-pin) 26 (28-pin) 31 (32-pin) 29 (30-pin) 27 (28-pin) 4 (32-pin) 4 (30-pin) 4 (28-pin) During Programming I/O I/O Function Serial data pin (output when reading, Input when writing) Input and push-pull output port can be assigned Serial clock pin (input only pin)
P3.2
SCLK
I
TEST
VPP
I
Power supply pin for flash ROM cell writing (indicates that MTP enters into the writing mode). When 12.5 V is applied, MTP is in writing mode and when 5 V is applied, MTP is in reading mode. (Option)
P0.2
RESETB
7 (32-pin) 7 (30-pin) 7 (28-pin) 32/1 (32-pin) 30/1 (30-pin) 28/1 (28-pin)
I
VDD/VSS
VDD/VSS
I
Logic power supply pin.
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MTP
S3C9498/F9498
NOTES
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S3C9498/F9498
DEVELOPMENT TOOLS
21
OVERVIEW
SHINE
DEVELOPMENT TOOLS
Samsung provides a powerful and easy-to-use development support system on a turnkey basis. The development support system is composed of a host system, debugging tools, and supporting software. For a host system, any standard computer that employs Win95/98/2000 as its operating system can be used. A sophisticated debugging tool is provided both in hardware and software: the powerful in-circuit emulator, SMDS2+ or SK-1000, for the S3C7-, S3C9-, and S3C8- microcontroller families. SMDS2+ is a newly improved version of SMDS2, and SK-1000 is supported by a third party tool vendor. Samsung also offers supporting software that includes, debugger, an assembler, and a program for setting options.
Samsung Host Interface for In-Circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. It has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be easily sized, moved, scrolled, highlighted, added, or removed. SASM The SASM takes a source file containing assembly language statements and translates them into a corresponding source code, an object code and comments. The SASM supports macros and conditional assembly. It runs on the MS-DOS operating system. As it produces the re-locatable object codes only, the user should link object files. Object files can be linked with other object files and loaded into memory. SASM requires a source file and an auxiliary register file (device_name.reg) with device specific information. SAMA ASSEMBLER The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generating an object code in the standard hexadecimal format. Assembled program codes include the object code used for ROM data and required In-circuit emulators program control data. To assemble programs, SAMA requires a source file and an auxiliary definition (device_name.def) file with device specific information. HEX2ROM HEX2ROM file generates a ROM code from a HEX file which is produced by the assembler. A ROM code is needed to fabricate a microcontroller which has a mask ROM. When generating a ROM code (.OBJ file) by HEX2ROM, the value "FF" is automatically filled into the unused ROM area, up to the maximum ROM size of the target device.
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DEVELOPMENT TOOLS
S3C9498/F9498
TARGET BOARDS Target boards are available for all the S3C9-series microcontrollers. All the required target system cables and adapters are included with the device-specific target board. TB9498 is a specific target board for the S3C9498/F9498 development
IBM-PC AT or Compatible
RS-232C
Emulator (SMDS2+ or SK-1000)
EPROM Writer Unit
Target Application System
RAM Break/Display Unit Probe Adapter Bus Trace/Timer Unit
SAM9 Base Unit
POD
TB9498 Target Board EVA Chip
Power Supply Unit
Figure 21-1. SMDS+ or SK-1000 Product Configuration
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S3C9498/F9498
DEVELOPMENT TOOLS
TB9498 TARGET BOARD The TB9498 target board is used for the S3C9498/F9498 microcontrollers. It is supported by the SK-1000/SMDS2+ development systems.
TB9498
To User_V CC Off RESET U2 74HC11 GND 25 100 - Pin Connector J101 1 CN1 DIP SW 144 QFP S3E9490 EVA Chip 40 - Pin Connector 20 21 SMxxxx 40 1 SMDS 2 SMDS2+ On Idle + Stop + VCC
Figure 21-2. TB9498 Target Board Configuration
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DEVELOPMENT TOOLS
S3C9498/F9498
Table 21-1. Power Selection Settings for TB9498 "To User_Vcc" Settings
To user_Vcc off on
Operating Mode
Comments The SK-1000/SMDS2+ main board supplies VCC to the target board (evaluation chip) and the target system.
TB9498
External VCC VSS Target System
VCC SK-1000/SMDS2+
To user_Vcc off on
TB9498
Extern al VC C V SS T arget Syste m
The SK-1000/SMDS2+ main board supplies VCC only to the target board (evaluation chip). The target system must have its own power supply.
VCC SK-1000/SMDS2+
NOTE: The following symbol in the "To User_Vcc" Setting column indicates the electrical short (off) configuration:
SMDS2+ Selection (SAM8) In order to write data into program memory that is available in SMDS2+, the target board should be selected to be for SMDS2+ through a switch as follows. Otherwise, the program memory writing function is not available. Table 21-2. The SMDS2+ Tool Selection Setting "SW1" Setting
SMDS SMDS2+
Operating Mode
R/W* SMDS2+
R/W*
Target System
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S3C9498/F9498
DEVELOPMENT TOOLS
ON OFF 3EH.7 3FH.0
ON OFF
Low High
NOTE: About EVA chip, smart option is determined by DIP switch not software.
Figure 21-3. DIP Switch for Smart Option
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DEVELOPMENT TOOLS
S3C9498/F9498
J101
VSS XOUT XIN TEST RxD/P0.0 TxD/P0.1 RESETB/P0.2 AVREF INT0/ADC0/P1.0 INT1/ADC1/P1.1 ADC2/P1.2 ADC3/P1.3 ADC4/P1.4 ADC5/P1.5 P3.3 P3.4 NC NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VDD P3.2/SCK P3.1/SO P3.0/SI P2.7/PWM P2.6/T0CAP P2.5/T0OUT P2.4/T0CK P2.3/TBOUT P2.2/TACAP P2.1/TACK P2.0/TAOUT P1.7/ADC7 P1.6/ADC6/TDOUT P3.6 P3.5 NC NC NC NC
Figure 21-4. 44-Pin Connector for TB9498
40-PIN DIP S O C K E T
Target Board J101 1 40
Target System
1
40
Figure 21-5. S3C9498/F9498 Probe Adapter for 40pin Connector Package
40 - Pin Connector
40 - Pin Connector
Part Name: AS20D Order Cods: SM6304
20
21
20
21
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